summaryrefslogtreecommitdiff
path: root/shared-core
AgeCommit message (Collapse)Author
2007-02-25Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestlineNian Wu
2007-02-25drm: remove unnecessary NULL checks, and fix some indents..Jakob Bornecrantz
2007-02-16Simple fence object sample driver for via, based on idling the GPU.Thomas Hellstrom
Buffer object driver for via. Some changes to buffer object driver callbacks. Improve fence flushing.
2007-02-15Initial support for fence object classes.Thomas Hellstrom
(Fence objects belonging to different command submission mechanisms).
2007-02-14Merge branch 'ttm-vram-0-1-branch'Thomas Hellstrom
2007-02-14Remove an intel-specific hack and replace it with a fence driver callback.Thomas Hellstrom
2007-02-14nouveau: fix the build on big endian (thanks CyberFoxx)Stephane Marchesin
2007-02-14nouveau: fix memory initialization with multiple cards.B. Rathmann
2007-02-13Bugzilla Bug #9457Thomas Hellstrom
Add refcounting of user waiters to the DRM hardware lock, so that we can use the DRM_LOCK_CONT flag more conservatively. Also add a kernel waiter refcount that if nonzero transfers the lock for the kernel context, when it is released. This is useful when waiting for idle and can be used for very simple fence object driver implementations for the new memory manager. It also resolves the AIGLX startup deadlock for the sis and the via drivers. i810, i830 still require that the hardware lock is really taken so the deadlock remains for those two. I'm not sure about ffb. Anyone familiar with that code?
2007-02-13i915: Add 965GM pci id updateWang Zhenyu
2007-02-12Update flags and comments.Thomas Hellstrom
2007-02-09I915 accelerated blit copy functional.Thomas Hellstrom
Fixed - to System memory copies are implemented by flipping in a cache-coherent TTM, blitting to it, and then flipping it out.
2007-02-07Warning fix: correct type of i915_mmio argument.Eric Anholt
2007-02-07Define __iomem for systems without it.Eric Anholt
2007-02-07Add chip family flags to i915 driver, and fix a missing '"' in mach64 ID list.Eric Anholt
2007-02-07Checkpoint commit.Thomas Hellstrom
Flag handling and memory type selection cleanup. glxgears won't start.
2007-02-06Implement a policy for selecting memory types.Thomas Hellstrom
2007-02-06nouveau: more work on the nv04 context switch code.Stephane Marchesin
2007-02-03nouveau: and of course, I was missing the last nv04 piece.Stephane Marchesin
2007-02-03nouveau: plugin the nv04 graph init function.Stephane Marchesin
2007-02-03nouveau: cleanup the nv04 pgraph save/restore mechanism.Stephane Marchesin
2007-02-03nouveau: fix nv04 graph routines for new register names.Stephane Marchesin
2007-02-03nouveau: rename registers to their proper names.Stephane Marchesin
2007-02-03nouveau: add NV04 registers required for PGRAPH context switching.Stephane Marchesin
2007-02-02nouveau: nv ctx switch opps the size of array was wrongMatthieu Castet
2007-02-02nouveau: nv10 ctx switch, some regs are nv17+ onlyMatthieu Castet
2007-02-02via: Try to improve command-buffer chaining.Thomas Hellstrom
Bump driver date and patchlevel.
2007-02-02Disable AGP DMA for chips with the new 3D engine.Thomas Hellstrom
2007-01-31memory manager: Make device driver aware of different memory types.Thomas Hellstrom
Memory types are either fixed (on-card or pre-bound AGP) or not fixed (dynamically bound) to an aperture. They also carry information about: 1) Whether they can be mapped cached. 2) Whether they are at all mappable. 3) Whether they need an ioremap to be accessible from kernel space. In this way VRAM memory and, for example, pre-bound AGP appear identical to the memory manager. This also makes support for unmappable VRAM simple to implement.
2007-01-28nouveau: determine chipset type at startup, instead of every time we use it.Ben Skeggs
2007-01-26make works ctx switch on nv10.Matthieu Castet
2007-01-26nouveau: oops, wrong indexing in nv17 regsPatrice Mandin
2007-01-26nouveau: read gpu type oncePatrice Mandin
2007-01-26nouveau: only save/restore nv17 regs on nv17,18 hwPatrice Mandin
2007-01-26nouveau: add extra pgraph registersPatrice Mandin
2007-01-26nouveau: add some nv10 pgraph definesPatrice Mandin
2007-01-25nouveau: simplify and fix BIG_ENDIAN flagsPatrice Mandin
2007-01-25nouveau: nv4c default contextBen Skeggs
2007-01-25nouveau: always print nsource/nstatus regs on PGRAPH errorsBen Skeggs
2007-01-24vblank interrupt fixZou Nan hai
2007-01-19nouveau: fix getparam from 32-bit client on 64-bit kernelBen Skeggs
2007-01-19nouveau: re-add 6150 Go pciid (0x0244)Ben Skeggs
2007-01-18nouveau: cleanup nv30_graph.cJeremy Kolb
2007-01-18nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH switching.Jeremy Kolb
2007-01-18add missing quadro idDave Jones
2007-01-17nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet.Jeremy Kolb
Hook into nv20 pgraph switching functions (they're identical for nv3x). Actually call nv30_pgraph_context_init so the ctx_table is allocated. Thanks to Carlos Martin for the help.
2007-01-14nouveau: opps nv20 ctx ramin size was wrongMatthieu Castet
2007-01-13nouveau: opps restored the wrong channelMatthieu Castet
2007-01-13nouveau: nv20 graph ctx switch.Matthieu Castet
Untested...
2007-01-13nouveau: first step to make graph ctx worksMatthieu Castet
It is still not working, but now we could use some 3D commands without needed to run nvidia blob before.
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-08 06:25:42 +0000