renesas/drm.git - libdrm, cloned from git://anongit.freedesktop.org/mesa/drm

Age	Commit message (Collapse)	Author
2007-07-11	NV50 will not attempt to use PCIGART now	Arthur Huillet

2007-07-11	fixed bug that prevented PCIE cards from actually using PCIGART - NV50 will ↵	Arthur Huillet
	probably still have a problem
2007-07-11	nouveau/nv50: G80 fixes.	Ben Skeggs
	Again, no hardware, so no idea if it'll even work yet. I understand how the PRAMIN setup works now, un-hardcoding stuff will come "RealSoonNow(tm)".
2007-07-11	nouveau: Some checks on userspace object handles.	Ben Skeggs

2007-07-11	Merge branch 'master' into cleanup	Dave Airlie
	Conflicts: libdrm/xf86drm.c linux-core/drm_bo.c linux-core/drm_fence.c
2007-07-11	Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel.	Arthur Huillet

2007-07-09	Fix ioctl types.	Ian Romanick
	I had moved code from xgi_drv.h to xgi_drm.h before changing the ioctl types for XGI_IOCTL_(FB\|PCIE)_ALLOC.
2007-07-09	Move types shared with user mode to xgi_drm.h.	Ian Romanick

2007-07-09	nouveau: Allocate mappable VRAM for notifiers..	Ben Skeggs

2007-07-09	nouveau: Don't be so strict on <NV50	Ben Skeggs

2007-07-09	nouveau: Avoid oops	Ben Skeggs
	Turns out lastclose() gets called even if firstopen() has never been...
2007-07-09	nouveau/nv50: Initial channel/object support	Ben Skeggs
	Should be OK on G84 for a single channel, multiple channels almost work. Untested on G80.
2007-07-09	nouveau: enable reporting for all PFIFO/PGRAPH irqs	Ben Skeggs

2007-07-09	nouveau: rewrite gpu object code	Ben Skeggs
	Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-06	radeon: Improve vblank counter.	Michel Dänzer
	The frame counter seems to increase only at the end of vertical blank, so we need to add 1 while in vertical blank.
2007-07-03	One more spinlock initializer cleanup.	Michel Dänzer

2007-06-29	nouveau: small RAMFC cleanups	Ben Skeggs

2007-06-28	nouveau: Hack around possible Xv blit adaptor breakage	Ben Skeggs

2007-06-28	nouveau/nv10: Fix earlier NV1x chips	Ben Skeggs
	Can't use nv04 code for them, since an extra field was inserted into RAMFC after DMA_PUT/GET.
2007-06-28	nouveau: never touch PRAMIN with NV_WRITE, cleanup RAMHT code a bit	Ben Skeggs

2007-06-28	nouveau: simplify PRAMIN access	Ben Skeggs

2007-06-28	nouveau: name some regs	Ben Skeggs

2007-06-28	nouveau/nv50: skeletal backend	Ben Skeggs

2007-06-28	nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7)	Ben Skeggs
	For various reasons, this ioctl was a bad idea. At channel creation we now automatically create DMA objects covering available VRAM and GART memory, where the client used to do this themselves. However, there is still a need to be able to create DMA objects pointing at specific areas of memory (ie. notifiers). Each channel is now allocated a small amount of memory from which a client can suballocate things (such as notifiers), and have a DMA object created which covers the suballocated area. The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-28	nouveau/nv04: Set NV_PFIFO_CACHE1_PUSH1 correctly + small tweaks	Ben Skeggs

2007-06-26	More 64-bit padding.	Thomas Hellstrom

2007-06-26	Add support SiS based XGI chips to SiS DRM.	Ian Romanick

2007-06-25	nouveau: NV49/NV4B PGRAPH setup from jb17bsome and stephan_2303	Ben Skeggs

2007-06-24	nouveau: kill some dead code	Ben Skeggs

2007-06-24	nouveau: NV04/NV10/NV20 PGRAPH engtab functions	Ben Skeggs
	NV04/NV10 load_context()/save_context() are stubs. I don't know enough about how they work to implement them sanely. The "old" context_switch() code remains hooked up, so it shouldn't break anything. NV20 will probably break if load_context() works. No inital context values are filled in, so when the first channel is created PGRAPH will probably end up having its state zeroed. Some setup from nv20_graph_init() will probably need to be moved to the per-channel context setup.
2007-06-24	nouveau: NV3X PGRAPH engtab functions	Ben Skeggs

2007-06-24	nouveau: NV1X/2X/3X PFIFO engtab functions	Ben Skeggs
	Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC entry size.
2007-06-24	nouveau: NV04 PFIFO engtab functions	Ben Skeggs

2007-06-24	nouveau: NV4X PGRAPH engtab functions	Ben Skeggs

2007-06-24	nouveau: NV4X PFIFO engtab functions	Ben Skeggs

2007-06-24	nouveau: split PFIFO/PGRAPH context creation	Ben Skeggs

2007-06-24	nouveau: (mostly) hook up put_base again	Ben Skeggs

2007-06-24	nouveau: prototype PFIFO/PGRAPH engtab API	Ben Skeggs

2007-06-24	nouveau: rename engtab functions	Ben Skeggs

2007-06-22	Merge branch 'vblank-rework' into vblank	Jesse Barnes

2007-06-22	more vblank rework	Jesse Barnes
	- use a timer for disabling vblank events to avoid enable/disable calls too often - make i915 work with pre-965 chips again (would like to structure this better, but this hack works on my test system)
2007-06-22	radeon: Acknowledge all interrupts we're interested in.	Michel Dänzer
	Failure to do so was probably the root cause of fd.o bug 11287.
2007-06-22	drm_modeset_ctl_t fixes.	Michel Dänzer
	s/u64/drm_u64_t/ to allow userspace code using drm.h to compile. Move 64 bit arg member to the beginning to avoid alignment issues with 32 bit userspace on 64 bit kernels.
2007-06-22	Remove mask parameter from radeon_acknowledge_irqs().	Michel Dänzer
	Simply always acknowledge all interrupts we're interested in, to avoid hard hangs when an unexpected interrupt is flagged.
2007-06-21	Merge branch 'vblank-rework' into vblank	Jesse Barnes

2007-06-21	RADEON: fix race in vblank interrupt handling	Jesse Barnes
	It's possible that we disable vblank interrupts and clear the corresponding flag in irq_enable_reg, but receive an interrupt at just the wrong time, causing us to not ack it properly, nor report to the core kernel that it was handled. Fix that case by always handling vblank interrupts, even if the irq_enable_reg field is clear.
2007-06-21	r300: Synchronized the register defines file; documentation changes.	Oliver McFadden

2007-06-21	r300: Allow writes to R300_VAP_PVS_WAITIDLE.	Oliver McFadden

2007-06-18	Remove broken CRTC enable checks and incorrect user irq enable in set_pipe	Jesse Barnes
	routine.
2007-06-18	radeon: VBlank rework fixups.	Michel Dänzer
	Fix range of frame counter registers. Use DRM_ERR() instead of Linux specific error codes in shared code. Remove duplicate register definitions and superfluous local variables.