Age | Commit message (Collapse) | Author | |
---|---|---|---|
2007-07-11 | fixed bug that prevented PCIE cards from actually using PCIGART - NV50 will ↵ | Arthur Huillet | |
probably still have a problem | |||
2007-07-11 | nouveau/nv50: G80 fixes. | Ben Skeggs | |
Again, no hardware, so no idea if it'll even work yet. I understand how the PRAMIN setup works now, un-hardcoding stuff will come "RealSoonNow(tm)". | |||
2007-07-11 | nouveau: Some checks on userspace object handles. | Ben Skeggs | |
2007-07-11 | Merge branch 'master' into cleanup | Dave Airlie | |
Conflicts: libdrm/xf86drm.c linux-core/drm_bo.c linux-core/drm_fence.c | |||
2007-07-11 | Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel. | Arthur Huillet | |
2007-07-09 | nouveau: Allocate mappable VRAM for notifiers.. | Ben Skeggs | |
2007-07-09 | nouveau: Don't be so strict on <NV50 | Ben Skeggs | |
2007-07-09 | nouveau: Avoid oops | Ben Skeggs | |
Turns out lastclose() gets called even if firstopen() has never been... | |||
2007-07-09 | nouveau/nv50: Initial channel/object support | Ben Skeggs | |
Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80. | |||
2007-07-09 | nouveau: enable reporting for all PFIFO/PGRAPH irqs | Ben Skeggs | |
2007-07-09 | nouveau: rewrite gpu object code | Ben Skeggs | |
Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object. | |||
2007-07-03 | One more spinlock initializer cleanup. | Michel Dänzer | |
2007-06-29 | nouveau: small RAMFC cleanups | Ben Skeggs | |
2007-06-28 | nouveau: Hack around possible Xv blit adaptor breakage | Ben Skeggs | |
2007-06-28 | nouveau/nv10: Fix earlier NV1x chips | Ben Skeggs | |
Can't use nv04 code for them, since an extra field was inserted into RAMFC after DMA_PUT/GET. | |||
2007-06-28 | nouveau: never touch PRAMIN with NV_WRITE, cleanup RAMHT code a bit | Ben Skeggs | |
2007-06-28 | nouveau: simplify PRAMIN access | Ben Skeggs | |
2007-06-28 | nouveau: name some regs | Ben Skeggs | |
2007-06-28 | nouveau/nv50: skeletal backend | Ben Skeggs | |
2007-06-28 | nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7) | Ben Skeggs | |
For various reasons, this ioctl was a bad idea. At channel creation we now automatically create DMA objects covering available VRAM and GART memory, where the client used to do this themselves. However, there is still a need to be able to create DMA objects pointing at specific areas of memory (ie. notifiers). Each channel is now allocated a small amount of memory from which a client can suballocate things (such as notifiers), and have a DMA object created which covers the suballocated area. The NOTIFIER_ALLOC ioctl exposes this functionality. | |||
2007-06-28 | nouveau/nv04: Set NV_PFIFO_CACHE1_PUSH1 correctly + small tweaks | Ben Skeggs | |
2007-06-26 | More 64-bit padding. | Thomas Hellstrom | |
2007-06-26 | Add support SiS based XGI chips to SiS DRM. | Ian Romanick | |
2007-06-25 | nouveau: NV49/NV4B PGRAPH setup from jb17bsome and stephan_2303 | Ben Skeggs | |
2007-06-24 | nouveau: kill some dead code | Ben Skeggs | |
2007-06-24 | nouveau: NV04/NV10/NV20 PGRAPH engtab functions | Ben Skeggs | |
NV04/NV10 load_context()/save_context() are stubs. I don't know enough about how they work to implement them sanely. The "old" context_switch() code remains hooked up, so it shouldn't break anything. NV20 will probably break if load_context() works. No inital context values are filled in, so when the first channel is created PGRAPH will probably end up having its state zeroed. Some setup from nv20_graph_init() will probably need to be moved to the per-channel context setup. | |||
2007-06-24 | nouveau: NV3X PGRAPH engtab functions | Ben Skeggs | |
2007-06-24 | nouveau: NV1X/2X/3X PFIFO engtab functions | Ben Skeggs | |
Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC entry size. | |||
2007-06-24 | nouveau: NV04 PFIFO engtab functions | Ben Skeggs | |
2007-06-24 | nouveau: NV4X PGRAPH engtab functions | Ben Skeggs | |
2007-06-24 | nouveau: NV4X PFIFO engtab functions | Ben Skeggs | |
2007-06-24 | nouveau: split PFIFO/PGRAPH context creation | Ben Skeggs | |
2007-06-24 | nouveau: (mostly) hook up put_base again | Ben Skeggs | |
2007-06-24 | nouveau: prototype PFIFO/PGRAPH engtab API | Ben Skeggs | |
2007-06-24 | nouveau: rename engtab functions | Ben Skeggs | |
2007-06-22 | radeon: Acknowledge all interrupts we're interested in. | Michel Dänzer | |
Failure to do so was probably the root cause of fd.o bug 11287. | |||
2007-06-21 | r300: Synchronized the register defines file; documentation changes. | Oliver McFadden | |
2007-06-21 | r300: Allow writes to R300_VAP_PVS_WAITIDLE. | Oliver McFadden | |
2007-06-18 | r300: Registers 0x2220-0x2230 are known as R300_VAP_CLIP_X_0-R300_VAP_CLIP_Y_1. | Oliver McFadden | |
2007-06-18 | r300: Synchronized the register defines file again. | Oliver McFadden | |
2007-06-15 | i915: Fix handling of breadcrumb counter wraparounds. | Michel Dänzer | |
2007-06-12 | Fix some obvious bugs. | Thomas Hellstrom | |
2007-06-12 | Try to make buffer object / fence object ioctl args 64-bit safe. | Thomas Hellstrom | |
Introduce tile members for future tiled buffer support. Allow user-space to explicitly define a fence-class. Remove the implicit fence-class mechanism. 64-bit wide buffer object flag member. | |||
2007-06-08 | r300: Added the CP maximum fetch size and ring rptr update variables. | Oliver McFadden | |
2007-06-05 | r300: Small correction to the previous commit. | Oliver McFadden | |
2007-06-05 | r300: Document more of the RADEON_RBBM_STATUS register. | Alex Deucher | |
2007-06-05 | Add support for the G33, Q33, and Q35 chipsets. | Wang Zhenyu | |
These require that the status page be referenced by a pointer in GTT, rather than phsyical memory. So, we have the X Server allocate that memory and tell us the address, instead. | |||
2007-06-04 | nouveau: fix RAMHT wrapping | Maurice van der Pot | |
2007-06-03 | radeon: refine irq acking for vbl on crtc 2 | Dave Airlie | |
2007-06-03 | Revert "move i915 to new drm_wait_on function" | root | |
This reverts commit feb68037784ac09e333a321d294fdb2d8c57a4c8. This was a bad idea, the macro is actually a bit harder to convert to a static for the other use cases |