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path: root/shared-core/r128_cce.c
AgeCommit message (Expand)Author
2008-01-03drm: cleanup DRM_DEBUG() parametersMárton Németh
2007-11-05drm: remove lots of spurious whitespace.Dave Airlie
2007-07-20Replace DRM_IOCTL_ARGS with (dev, data, file_priv) and remove DRM_DEVICE.Eric Anholt
2007-07-20Replace filp in ioctl arguments with drm_file *file_priv.Eric Anholt
2007-07-20Remove DRM_ERR OS macro.Eric Anholt
2007-07-16drm: remove drmP.h internal typedefsDave Airlie
2007-07-16drm: detypedef drm.h and fixup all problemsDave Airlie
2007-04-28remove DRM_GETSAREA and replace with drm_getsarea functionDave Airlie
2007-04-09radeon: add support for reverse engineered xpress200mDave Airlie
2007-03-04ati: make pcigart code able to handle variable size PCI GART apertureDave Airlie
2005-11-28Assert an MIT copyright on sis_drm.h, since one was lacking and I createdEric Anholt
2005-11-08Catch FreeBSD up to the pcie gart changes. Required minor modification toEric Anholt
2005-09-11Add GART in FB support for ati pcigart, and PCIE support for r300Dave Airlie
2005-08-16add Egberts 32/64 bit patch (its in kernel already...)Dave Airlie
2005-07-20Add latest r300 support from r300.sf.net CVS. Patch submitted by volodya,Eric Anholt
2005-02-01cleanup patch from Adrian Bunk <bunk@stusta.de>Dave Airlie
2004-10-06Revert back to drm_order() instead of using kernel get_order(). TheJon Smirl
2004-09-30Lindent of core build. Drivers checked for no binary diffs. A few filesJon Smirl
2004-09-30Move things around to reduce public symbols and even out files. Switch toJon Smirl
2004-09-27First check in for DRM that splits core from personality modulesJon Smirl
2004-08-24Merged drmfntbl-0-0-2Dave Airlie
2004-08-23set pointers to NULL after freeing, remove some extra debuggingDave Airlie
2004-08-17Merged drmfntbl-0-0-1Dave Airlie
2004-07-25sync up with current 2.6 kernel bk tree - mostly __user annotationsDave Airlie
2003-12-16Don't ioremap the framebuffer area. The ioremapped area wasn't used byEric Anholt
2003-11-05- Tie the DRM to a specific device: setunique no longer succeeds when givenEric Anholt
2003-10-17- Move IRQ functions from drm_dma.h to new drm_irq.h and disentangle themEric Anholt
2003-10-16Introduce COMMIT_RING() as in radeon DRM, stop using error prone writebackMichel Daenzer
2003-08-18Make r128_do_wait_for_idle static, as it's only used in this file.Eric Anholt
2003-07-26Degrade uninformative error message to debug message, as in other driversMichel Daenzer
2003-07-26Add Rage 128 pageflipping support, defaults to off. DRM version bump toEric Anholt
2003-05-16Support AGP bridges where the AGP aperture can't be accessed directly byMichel Daenzer
2003-04-26Ensure driver has been initialized (dev_private != NULL) before installingLeif Delgass
2003-04-21Check for NULL map before calling DRM(ioremapfree) on cleanup. Prevents anLeif Delgass
2003-03-28merged drm-filp-0-1-branchKeith Whitwell
2003-03-25XFree86 4.3.0 mergeAlan Hourihane
2003-02-21Merge from bsd-4-0-0-branch.Eric Anholt
2002-08-29standardize use of __FUNCTION__ (Linus)Keith Whitwell
2002-07-05merged bsd-3-0-0-branchAlan Hourihane
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 07:20:24 +0000
">#define I830_UPLOAD_TEX0_CUBE 0x200 /* handled clientside */ #define I830_UPLOAD_TEX1_IMAGE 0x400 /* handled clientside */ #define I830_UPLOAD_TEX1_CUBE 0x800 /* handled clientside */ #define I830_UPLOAD_TEX2_IMAGE 0x1000 /* handled clientside */ #define I830_UPLOAD_TEX2_CUBE 0x2000 /* handled clientside */ #define I830_UPLOAD_TEX3_IMAGE 0x4000 /* handled clientside */ #define I830_UPLOAD_TEX3_CUBE 0x8000 /* handled clientside */ #define I830_UPLOAD_TEX_N_IMAGE(n) (0x100 << (n * 2)) #define I830_UPLOAD_TEX_N_CUBE(n) (0x200 << (n * 2)) #define I830_UPLOAD_TEXIMAGE_MASK 0xff00 #define I830_UPLOAD_TEX0 0x10000 #define I830_UPLOAD_TEX1 0x20000 #define I830_UPLOAD_TEX2 0x40000 #define I830_UPLOAD_TEX3 0x80000 #define I830_UPLOAD_TEX_N(n) (0x10000 << (n)) #define I830_UPLOAD_TEX_MASK 0xf0000 #define I830_UPLOAD_TEXBLEND0 0x100000 #define I830_UPLOAD_TEXBLEND1 0x200000 #define I830_UPLOAD_TEXBLEND2 0x400000 #define I830_UPLOAD_TEXBLEND3 0x800000 #define I830_UPLOAD_TEXBLEND_N(n) (0x100000 << (n)) #define I830_UPLOAD_TEXBLEND_MASK 0xf00000 #define I830_UPLOAD_TEX_PALETTE_N(n) (0x1000000 << (n)) #define I830_UPLOAD_TEX_PALETTE_SHARED 0x4000000 /* Indices into buf.Setup where various bits of state are mirrored per * context and per buffer. These can be fired at the card as a unit, * or in a piecewise fashion as required. */ /* Destbuffer state * - backbuffer linear offset and pitch -- invarient in the current dri * - zbuffer linear offset and pitch -- also invarient * - drawing origin in back and depth buffers. * * Keep the depth/back buffer state here to acommodate private buffers * in the future. */ #define I830_DESTREG_CBUFADDR 0 /* Invarient */ #define I830_DESTREG_DBUFADDR 1 #define I830_DESTREG_DV0 2 #define I830_DESTREG_DV1 3 #define I830_DESTREG_SENABLE 4 #define I830_DESTREG_SR0 5 #define I830_DESTREG_SR1 6 #define I830_DESTREG_SR2 7 #define I830_DESTREG_DR0 8 #define I830_DESTREG_DR1 9 #define I830_DESTREG_DR2 10 #define I830_DESTREG_DR3 11 #define I830_DESTREG_DR4 12 #define I830_DEST_SETUP_SIZE 13 /* Context state */ #define I830_CTXREG_STATE1 0 #define I830_CTXREG_STATE2 1 #define I830_CTXREG_STATE3 2 #define I830_CTXREG_STATE4 3 #define I830_CTXREG_STATE5 4 #define I830_CTXREG_IALPHAB 5 #define I830_CTXREG_STENCILTST 6 #define I830_CTXREG_ENABLES_1 7 #define I830_CTXREG_ENABLES_2 8 #define I830_CTXREG_AA 9 #define I830_CTXREG_FOGCOLOR 10 #define I830_CTXREG_BLENDCOLR0 11 #define I830_CTXREG_BLENDCOLR 12 /* Dword 1 of 2 dword command */ #define I830_CTXREG_VF 13 #define I830_CTXREG_VF2 14 #define I830_CTXREG_MCSB0 15 #define I830_CTXREG_MCSB1 16 #define I830_CTX_SETUP_SIZE 17 /* Texture state (per tex unit) */ #define I830_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (6 dwords) */ #define I830_TEXREG_MI1 1 #define I830_TEXREG_MI2 2 #define I830_TEXREG_MI3 3 #define I830_TEXREG_MI4 4 #define I830_TEXREG_MI5 5 #define I830_TEXREG_MF 6 /* GFX_OP_MAP_FILTER */ #define I830_TEXREG_MLC 7 /* GFX_OP_MAP_LOD_CTL */ #define I830_TEXREG_MLL 8 /* GFX_OP_MAP_LOD_LIMITS */ #define I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS */ #define I830_TEX_SETUP_SIZE 10 #define I830_FRONT 0x1 #define I830_BACK 0x2 #define I830_DEPTH 0x4 #endif /* _I830_DEFINES_ */ typedef struct _drm_i830_init { enum { I830_INIT_DMA = 0x01, I830_CLEANUP_DMA = 0x02 } func; unsigned int mmio_offset; unsigned int buffers_offset; int sarea_priv_offset; unsigned int ring_start; unsigned int ring_end; unsigned int ring_size; unsigned int front_offset; unsigned int back_offset; unsigned int depth_offset; unsigned int w; unsigned int h; unsigned int pitch; unsigned int pitch_bits; unsigned int back_pitch; unsigned int depth_pitch; unsigned int cpp; } drm_i830_init_t; /* Warning: If you change the SAREA structure you must change the Xserver * structure as well */ typedef struct _drm_i830_tex_region { unsigned char next, prev; /* indices to form a circular LRU */ unsigned char in_use; /* owned by a client, or free? */ int age; /* tracked by clients to update local LRU's */ } drm_i830_tex_region_t; typedef struct _drm_i830_sarea { unsigned int ContextState[I830_CTX_SETUP_SIZE]; unsigned int BufferState[I830_DEST_SETUP_SIZE]; unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE]; unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE]; unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT]; unsigned int Palette[2][256]; unsigned int dirty; unsigned int nbox; drm_clip_rect_t boxes[I830_NR_SAREA_CLIPRECTS]; /* Maintain an LRU of contiguous regions of texture space. If * you think you own a region of texture memory, and it has an * age different to the one you set, then you are mistaken and * it has been stolen by another client. If global texAge * hasn't changed, there is no need to walk the list. * * These regions can be used as a proxy for the fine-grained * texture information of other clients - by maintaining them * in the same lru which is used to age their own textures, * clients have an approximate lru for the whole of global * texture space, and can make informed decisions as to which * areas to kick out. There is no need to choose whether to * kick out your own texture or someone else's - simply eject * them all in LRU order. */ drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS+1]; /* Last elt is sentinal */ int texAge; /* last time texture was uploaded */ int last_enqueue; /* last time a buffer was enqueued */ int last_dispatch; /* age of the most recently dispatched buffer */ int last_quiescent; /* */ int ctxOwner; /* last context to upload state */ int vertex_prim; } drm_i830_sarea_t; /* I830 specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ #define DRM_IOCTL_I830_INIT DRM_IOW( 0x40, drm_i830_init_t) #define DRM_IOCTL_I830_VERTEX DRM_IOW( 0x41, drm_i830_vertex_t) #define DRM_IOCTL_I830_CLEAR DRM_IOW( 0x42, drm_i830_clear_t) #define DRM_IOCTL_I830_FLUSH DRM_IO ( 0x43) #define DRM_IOCTL_I830_GETAGE DRM_IO ( 0x44) #define DRM_IOCTL_I830_GETBUF DRM_IOWR(0x45, drm_i830_dma_t) #define DRM_IOCTL_I830_SWAP DRM_IO ( 0x46) #define DRM_IOCTL_I830_COPY DRM_IOW( 0x47, drm_i830_copy_t) #define DRM_IOCTL_I830_DOCOPY DRM_IO ( 0x48) typedef struct _drm_i830_clear { int clear_color; int clear_depth; int flags; unsigned int clear_colormask; unsigned int clear_depthmask; } drm_i830_clear_t; /* These may be placeholders if we have more cliprects than * I830_NR_SAREA_CLIPRECTS. In that case, the client sets discard to * false, indicating that the buffer will be dispatched again with a * new set of cliprects. */ typedef struct _drm_i830_vertex { int idx; /* buffer index */ int used; /* nr bytes in use */ int discard; /* client is finished with the buffer? */ } drm_i830_vertex_t; typedef struct _drm_i830_copy_t { int idx; /* buffer index */ int used; /* nr bytes in use */ void *address; /* Address to copy from */ } drm_i830_copy_t; typedef struct drm_i830_dma { void *virtual; int request_idx; int request_size; int granted; } drm_i830_dma_t; #endif /* _I830_DRM_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 07:20:24 +0000