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path: root/shared-core/nouveau_state.c
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2008-03-13nv50: force channel vram access through vmBen Skeggs
If we ever want to be able to use the 3D engine we have no choice. It appears that the tiling setup (required for 3D on G8x) is in the page tables. The immediate benefit of this change however is that it's now not possible for a client to use the GPU to render over the top of important engine setup tables, which also live in VRAM. G8x VRAM size is limited to 512MiB at the moment, as we use a 1-1 mapping of real vram pages to their offset within the start of a channel's VRAM DMA object and only populate a single PDE for VRAM use.
2008-01-30nv40: some more nv67 changesBen Skeggs
With some luck the drm-side will be OK now for this chipset.
2008-01-21nouveau: don't forget NV80.Stephane Marchesin
2008-01-21nouveau: new card family for old card designs.Stephane Marchesin
2008-01-07nv50: hook up timer funcs...Ben Skeggs
2008-01-07Nouveau: ppc oops.Stephane Marchesin
2008-01-07Nouveau: move PPC bios copy to firstopen.Stephane Marchesin
2007-11-30nouveau: Properly identify NV40 and NV44 generation.Maarten Maathuis
2007-11-16nouveau: also mention the number of succcessfully copied bios bytes.Stephane Marchesin
2007-11-15nouveau: be verbose about PPC bios for now.Stephane Marchesin
2007-11-15nouveau: use get_property instead of of_get_property on pre-2.6.22 kernels.Stephane Marchesin
2007-11-15nouveau: Copy the PPC bios to RAMIN on init, that lets us do proper output ↵Stephane Marchesin
detection in user space.
2007-11-14Revert "nouveau: stub superioctl"Ben Skeggs
This reverts commit 2370ded79b4176d76cda1ec5f495fd33c2d566ed. Err.. didn't mean for that to slip in :)
2007-11-14Merge branch 'fifo-cleanup' into upstream-masterBen Skeggs
2007-11-14nouveau: funcs to determine active channel on PFIFO.Ben Skeggs
2007-11-14nouveau: stub superioctlBen Skeggs
2007-11-05drm: remove lots of spurious whitespace.Dave Airlie
Kernel "cleanfile" script run.
2007-11-05nouveau: crappy ttm mm init, disabled for now.Ben Skeggs
2007-10-28nouveau: don't touch PMC_BOOT_1 on x86, it seems to be undefined on some ↵Stephane Marchesin
early cards.
2007-10-14nouveau: PPC fixes. These regs are very touchy.Stephane Marchesin
2007-10-10nouveau: PMC_BOOT_1 was not mapped.Maarten Maathuis
2007-10-10nouveau: try to fix big endian.Stephane Marchesin
2007-10-07nouveau: A char is signed, so it may overflow for >NV50.Maarten Maathuis
2007-10-04nouveau: Remove excess device classes.Maarten Maathuis
2007-10-04nouveau: Switch over to using PMC_BOOT_0 for card detection.Maarten Maathuis
2007-10-01nouveau: Fix dereferencing a NULL pointer when erroring out during ↵Maarten Maathuis
initialization.
2007-09-30nouveau: nv30 graph function renames, removed nv20_graph.cPekka Paalanen
All nv30 functions in nv30_graph.c that can be used on nv20 are renamed as accordingly. nv20 specific parts from nv20_graph.c are moved into nv30_graph.c.
2007-09-30nouveau: Make nv20 use the nv30 PGRAPH ctx functions.Pekka Paalanen
2007-08-31nouveau: give nv03 the last cut.Stephane Marchesin
2007-08-15nouveau/nv40: Fix channel scheduling.Ben Skeggs
Ensure NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLE gets set, otherwise channels will appear to "freeze" in some circumstances.
2007-08-10nouveau: Allow creation of gpuobjs before any other init has taken place.Ben Skeggs
2007-08-07nouveau : fix enable irq (in the previous code all irq were masked by engineMatthieu Castet
init after irq_postinstall)
2007-08-07nouveau: Init global gpuobj list early, unbreaks sgdma code.Ben Skeggs
2007-08-06nouveau: Give DRM its own gpu channelBen Skeggs
If your card doesn't have working context switching, it is now broken.
2007-08-06nouveau: Various internal and external API changesBen Skeggs
1. DRM_NOUVEAU_GPUOBJ_FREE Used to free GPU objects. The obvious usage case is for Gr objects, but notifiers can also be destroyed in the same way. GPU objects gain a destructor method and private data fields with this change, so other specialised cases (like notifiers) can be implemented on top of gpuobjs. 2. DRM_NOUVEAU_CHANNEL_FREE 3. DRM_NOUVEAU_CARD_INIT Ideally we'd do init during module load, but this isn't currently possible. Doing init during firstopen() is bad as X has a love of opening/closing the DRM many times during startup. Once the modesetting-101 branch is merged this can go away. IRQs are enabled in nouveau_card_init() now, rather than having the X server call drmCtlInstHandler(). We'll need this for when we give the kernel module its own channel. 4. DRM_NOUVEAU_GETPARAM Add CHIPSET_ID value, which will return the chipset id derived from NV_PMC_BOOT_0. 4. Use list_* in a few places, rather than home-brewed stuff.
2007-08-06nouveau: Pass channel struct around instead of channel id.Ben Skeggs
2007-07-20Replace DRM_IOCTL_ARGS with (dev, data, file_priv) and remove DRM_DEVICE.Eric Anholt
The data is now in kernel space, copied in/out as appropriate according to the This results in DRM_COPY_{TO,FROM}_USER going away, and error paths to deal with those failures. This also means that XFree86 4.2.0 support for i810 DRM is lost.
2007-07-20Replace filp in ioctl arguments with drm_file *file_priv.Eric Anholt
As a fallout, replace filp storage with file_priv storage for "unique identifier of a client" all over the DRM. There is a 1:1 mapping, so this should be a noop. This could be a minor performance improvement, as everything on Linux dereferenced filp to get file_priv anyway, while only the mmap ioctls went the other direction.
2007-07-20Remove DRM_ERR OS macro.Eric Anholt
This was used to make all ioctl handlers return -errno on linux and errno on *BSD. Instead, just return -errno in shared code, and flip sign on return from shared code to *BSD code.
2007-07-18nouveau: Make nouveau_wait_for_idle() read PTIMER.Pekka Paalanen
Following my nv28 kmmio dumps, nouveau_wait_for_idle() is modified to read PTIMER and NV03_PMC_ENABLE. Also a timeout based on PTIMER value is added, so wait_for_idle() cannot stall indefinitely (unless PTIMER is halted). The timeout was selected as 1 giga-ticks, which for me is 1s.
2007-07-18nouveau: Add read() method to Engine.timer.Pekka Paalanen
This is not called from anywhere, yet.
2007-07-17nouveau: G8x PCIEGARTBen Skeggs
Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART support for G8X using the current mm has been hacked on top of it.
2007-07-13nouveau: nuke internal typedefs, and drm_device_t use.Ben Skeggs
2007-07-11fixed bug that prevented PCIE cards from actually using PCIGART - NV50 will ↵Arthur Huillet
probably still have a problem
2007-07-11Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel.Arthur Huillet
2007-07-09nouveau: Avoid oopsBen Skeggs
Turns out lastclose() gets called even if firstopen() has never been...
2007-07-09nouveau/nv50: Initial channel/object supportBen Skeggs
Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-09nouveau: rewrite gpu object codeBen Skeggs
Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-06-28nouveau/nv10: Fix earlier NV1x chipsBen Skeggs
Can't use nv04 code for them, since an extra field was inserted into RAMFC after DMA_PUT/GET.
2007-06-28nouveau: simplify PRAMIN accessBen Skeggs