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path: root/shared-core/nouveau_state.c
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2007-10-14nouveau: PPC fixes. These regs are very touchy.Stephane Marchesin
2007-10-10nouveau: PMC_BOOT_1 was not mapped.Maarten Maathuis
2007-10-10nouveau: try to fix big endian.Stephane Marchesin
2007-10-07nouveau: A char is signed, so it may overflow for >NV50.Maarten Maathuis
2007-10-04nouveau: Remove excess device classes.Maarten Maathuis
2007-10-04nouveau: Switch over to using PMC_BOOT_0 for card detection.Maarten Maathuis
2007-10-01nouveau: Fix dereferencing a NULL pointer when erroring out during ↵Maarten Maathuis
initialization.
2007-09-30nouveau: nv30 graph function renames, removed nv20_graph.cPekka Paalanen
All nv30 functions in nv30_graph.c that can be used on nv20 are renamed as accordingly. nv20 specific parts from nv20_graph.c are moved into nv30_graph.c.
2007-09-30nouveau: Make nv20 use the nv30 PGRAPH ctx functions.Pekka Paalanen
2007-08-31nouveau: give nv03 the last cut.Stephane Marchesin
2007-08-15nouveau/nv40: Fix channel scheduling.Ben Skeggs
Ensure NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLE gets set, otherwise channels will appear to "freeze" in some circumstances.
2007-08-10nouveau: Allow creation of gpuobjs before any other init has taken place.Ben Skeggs
2007-08-07nouveau : fix enable irq (in the previous code all irq were masked by engineMatthieu Castet
init after irq_postinstall)
2007-08-07nouveau: Init global gpuobj list early, unbreaks sgdma code.Ben Skeggs
2007-08-06nouveau: Give DRM its own gpu channelBen Skeggs
If your card doesn't have working context switching, it is now broken.
2007-08-06nouveau: Various internal and external API changesBen Skeggs
1. DRM_NOUVEAU_GPUOBJ_FREE Used to free GPU objects. The obvious usage case is for Gr objects, but notifiers can also be destroyed in the same way. GPU objects gain a destructor method and private data fields with this change, so other specialised cases (like notifiers) can be implemented on top of gpuobjs. 2. DRM_NOUVEAU_CHANNEL_FREE 3. DRM_NOUVEAU_CARD_INIT Ideally we'd do init during module load, but this isn't currently possible. Doing init during firstopen() is bad as X has a love of opening/closing the DRM many times during startup. Once the modesetting-101 branch is merged this can go away. IRQs are enabled in nouveau_card_init() now, rather than having the X server call drmCtlInstHandler(). We'll need this for when we give the kernel module its own channel. 4. DRM_NOUVEAU_GETPARAM Add CHIPSET_ID value, which will return the chipset id derived from NV_PMC_BOOT_0. 4. Use list_* in a few places, rather than home-brewed stuff.
2007-08-06nouveau: Pass channel struct around instead of channel id.Ben Skeggs
2007-07-20Replace DRM_IOCTL_ARGS with (dev, data, file_priv) and remove DRM_DEVICE.Eric Anholt
The data is now in kernel space, copied in/out as appropriate according to the This results in DRM_COPY_{TO,FROM}_USER going away, and error paths to deal with those failures. This also means that XFree86 4.2.0 support for i810 DRM is lost.
2007-07-20Replace filp in ioctl arguments with drm_file *file_priv.Eric Anholt
As a fallout, replace filp storage with file_priv storage for "unique identifier of a client" all over the DRM. There is a 1:1 mapping, so this should be a noop. This could be a minor performance improvement, as everything on Linux dereferenced filp to get file_priv anyway, while only the mmap ioctls went the other direction.
2007-07-20Remove DRM_ERR OS macro.Eric Anholt
This was used to make all ioctl handlers return -errno on linux and errno on *BSD. Instead, just return -errno in shared code, and flip sign on return from shared code to *BSD code.
2007-07-18nouveau: Make nouveau_wait_for_idle() read PTIMER.Pekka Paalanen
Following my nv28 kmmio dumps, nouveau_wait_for_idle() is modified to read PTIMER and NV03_PMC_ENABLE. Also a timeout based on PTIMER value is added, so wait_for_idle() cannot stall indefinitely (unless PTIMER is halted). The timeout was selected as 1 giga-ticks, which for me is 1s.
2007-07-18nouveau: Add read() method to Engine.timer.Pekka Paalanen
This is not called from anywhere, yet.
2007-07-17nouveau: G8x PCIEGARTBen Skeggs
Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART support for G8X using the current mm has been hacked on top of it.
2007-07-13nouveau: nuke internal typedefs, and drm_device_t use.Ben Skeggs
2007-07-11fixed bug that prevented PCIE cards from actually using PCIGART - NV50 will ↵Arthur Huillet
probably still have a problem
2007-07-11Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel.Arthur Huillet
2007-07-09nouveau: Avoid oopsBen Skeggs
Turns out lastclose() gets called even if firstopen() has never been...
2007-07-09nouveau/nv50: Initial channel/object supportBen Skeggs
Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-09nouveau: rewrite gpu object codeBen Skeggs
Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-06-28nouveau/nv10: Fix earlier NV1x chipsBen Skeggs
Can't use nv04 code for them, since an extra field was inserted into RAMFC after DMA_PUT/GET.
2007-06-28nouveau: simplify PRAMIN accessBen Skeggs
2007-06-28nouveau/nv50: skeletal backendBen Skeggs
2007-06-28nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7)Ben Skeggs
For various reasons, this ioctl was a bad idea. At channel creation we now automatically create DMA objects covering available VRAM and GART memory, where the client used to do this themselves. However, there is still a need to be able to create DMA objects pointing at specific areas of memory (ie. notifiers). Each channel is now allocated a small amount of memory from which a client can suballocate things (such as notifiers), and have a DMA object created which covers the suballocated area. The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-24nouveau: NV04/NV10/NV20 PGRAPH engtab functionsBen Skeggs
NV04/NV10 load_context()/save_context() are stubs. I don't know enough about how they work to implement them sanely. The "old" context_switch() code remains hooked up, so it shouldn't break anything. NV20 will probably break if load_context() works. No inital context values are filled in, so when the first channel is created PGRAPH will probably end up having its state zeroed. Some setup from nv20_graph_init() will probably need to be moved to the per-channel context setup.
2007-06-24nouveau: NV3X PGRAPH engtab functionsBen Skeggs
2007-06-24nouveau: NV1X/2X/3X PFIFO engtab functionsBen Skeggs
Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC entry size.
2007-06-24nouveau: NV04 PFIFO engtab functionsBen Skeggs
2007-06-24nouveau: NV4X PGRAPH engtab functionsBen Skeggs
2007-06-24nouveau: NV4X PFIFO engtab functionsBen Skeggs
2007-06-24nouveau: rename engtab functionsBen Skeggs
2007-03-26nouveau: move card initialisation into the drmBen Skeggs
The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-13nouveau: make sure cmdbuf object gets destroyedBen Skeggs
2007-02-28nouveau: intrusive drm interface changesBen Skeggs
graphics objects: - No longer takes flags/dmaobj parameters, requires some major changes to the ddx to setup the object through the FIFO. This change is likely to cause breakages on some cards (tested on NV05,NV28,NV35, NV40 and NV4E). dma objects: - now takes a "class" parameter, not really used yet but we may need it at some point. - parameters are checked, so clients can't randomly create DMA objects pointing at whatever they feel like. misc: - Added FB_SIZE/AGP_SIZE getparams - Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR - Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't NOTIFICATION_PENDING.
2007-02-03nouveau: plugin the nv04 graph init function.Stephane Marchesin
2007-02-03nouveau: rename registers to their proper names.Stephane Marchesin
2007-01-28nouveau: determine chipset type at startup, instead of every time we use it.Ben Skeggs
2007-01-17nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet.Jeremy Kolb
Hook into nv20 pgraph switching functions (they're identical for nv3x). Actually call nv30_pgraph_context_init so the ctx_table is allocated. Thanks to Carlos Martin for the help.
2007-01-13nouveau: nv20 graph ctx switch.Matthieu Castet
Untested...
2007-01-13nouveau: first step to make graph ctx worksMatthieu Castet
It is still not working, but now we could use some 3D commands without needed to run nvidia blob before.
2007-01-09novueau: try resource 3 if resource 2 is 0 lengthDave Airlie
This happens on my NV43 PPC