renesas/drm.git - libdrm, cloned from git://anongit.freedesktop.org/mesa/drm

Age	Commit message (Collapse)	Author
2006-12-12	Port remaining NV4 RAMIN access from the ddx into the drm.	Ben Skeggs
	Should fix lockups seen on NV4 cards.
2006-12-03	Merge the pciid work.	Stephane Marchesin
	Add getparams for AGP and FB physical adresses. Fix the MEM_ALLOC issue properly. Fix context switches for nv44. Change the DRM version to 0.0.1.
2006-11-30	Use nouveau_mem.c to allocate RAMIN.	Ben Skeggs

2006-11-30	Wrap access to objects in RAMIN.	Ben Skeggs
	This will make it easier to support extra RAMIN in vram at a later point.
2006-11-28	For nv10, bit 16 of RAMFC need to be set for 64 bytes fifo context.	Matthieu Castet
	When cleaning a fifo, we shouldn't assume everybody use nv40 ;) Fill DMA_SUBROUTINE fill correct value.
2006-11-18	Only return FIFO number if the FIFO is marked as in use..	Ben Skeggs

2006-11-18	Check some return vals, fixes a couple of oopses.	Ben Skeggs

2006-11-17	Dump some useful info when a PGRAPH error occurs.	Ben Skeggs
	The "channel" detect doesn't work on my nv40, but the rest seems to produce sane info.
2006-11-14	Completely untested NV10/20/30 FIFO context switching changes.	Ben Skeggs

2006-11-14	Restructure initialisation a bit.	Ben Skeggs
	- Do important card init in firstopen - Give each channel it's own cmdbuf dma object - Move RAMHT config state to the same place as RAMRO/RAMFC - Make sure instance mem for objects is after RAM{FC,HT,RO}
2006-11-14	Hack around yet another "X restart borkage without nouveau.ko reload" problem.	Ben Skeggs
	On X init, PFIFO and PGRAPH are reset to defaults. This causes the GPU to loose the configuration done by the drm. Perhaps a CARD_INIT ioctl a proper solution to having this problem again in the future..
2006-11-06	fixup fifo size so it is page aligned	Dave Airlie

2006-10-18	Remove hack which delays activation of a additional channel. The previously ↵	Ben Skeggs
	active channel's state is saved to RAMFC before PFIFO gets clobbered.
2006-10-17	NV40: Now fifo ctx switching works for me..	Ben Skeggs
	Ok, I lied before.. it was a fluke it worked and required magic to repeat it.. It actually helps to fill in RAMFC entries in the correct place. The code also clears RAMIN entirely instead of just the hash-table.
2006-10-17	NV40: FIFO context switching now WorksForMe(tm)	Ben Skeggs

2006-10-17	Setup NV40 RAMFC (in wrong location.. but anyway), rearrange the RAMFC setup ↵	Ben Skeggs
	code a bit.
2006-10-14	Again more work on context switches. They work, sometimes. And when they do ↵	Stephane Marchesin
	they seem to screw up the PGRAPH state.
2006-10-14	Add the missing breaks.	Stephane Marchesin

2006-10-13	Fix the fifo context size on nv10, nv20 and nv30.	Stephane Marchesin

2006-10-14	Fix some randomness in activating a second channel on NV40 (odd GET/PUT ↵	Ben Skeggs
	vals). Ch 1 GET now advances, but no ctx_switch.
2006-10-12	Still more work on the context switching code.	Stephane Marchesin

2006-10-12	More work on the context switch code. Still doesn't work. I'm mostly ↵	Stephane Marchesin
	convinced it's an initialization issue.
2006-10-11	Context switching work.	Stephane Marchesin
	Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet). Removed the PFIFO_REINIT ioctl. I hope it's that a good idea... Requires the upcoming commit to the DDX.
2006-09-07	Fix second start of X server without module reload beforehand, and a couple ↵	Ben Skeggs
	of other fixes. - Mark the correct RAMIN slots as free (oops) - Remove a VRAM alloc that shouldn't have been there (oops) - Move HT init out of firstopen() and into dma_init() - Setup PFIFO_RAM{HT,FC,RO} in pfifo_init()
2006-09-03	Allow cmdbuf location(AGP,VRAM) and size to be configured.	Ben Skeggs

2006-08-30	Add stub {get,set}param ioctls.	Ben Skeggs

2006-08-27	initial import of nouveau code from nouveau CVS	Dave Airlie