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| author | Ben Skeggs <darktama@iinet.net.au> | 2006-11-30 08:35:42 +1100 |
|---|---|---|
| committer | Ben Skeggs <darktama@iinet.net.au> | 2006-11-30 08:35:42 +1100 |
| commit | b1a9a769711d83af8ab4c7ba4eec52a05a351533 (patch) | |
| tree | 287366255201c64d26f71bd96a0edddd83f4d7a4 /shared-core/nouveau_fifo.c | |
| parent | f48a7685bd7a241001cec89acd8cce6cdefa941e (diff) | |
Wrap access to objects in RAMIN.
This will make it easier to support extra RAMIN in vram at a later point.
Diffstat (limited to 'shared-core/nouveau_fifo.c')
| -rw-r--r-- | shared-core/nouveau_fifo.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index d67cdc3c..9ff0563c 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -247,7 +247,7 @@ static void nouveau_context_init(drm_device_t *dev, NV_WRITE(ctx_addr,init->put_base); NV_WRITE(ctx_addr+4,init->put_base); // that's what is done in nvosdk, but that part of the code is buggy so... - NV_WRITE(ctx_addr+8, cb_obj->instance >> 4); + NV_WRITE(ctx_addr+8, nouveau_chip_instance_get(dev, cb_obj->instance)); #ifdef __BIG_ENDIAN NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN); #else @@ -274,7 +274,8 @@ static void nouveau_nv10_context_init(drm_device_t *dev, */ RAMFC_WR(DMA_PUT , init->put_base); RAMFC_WR(DMA_GET , init->put_base); - RAMFC_WR(DMA_INSTANCE , cb_obj->instance >> 4); + RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev, + cb_obj->instance)); #ifdef __BIG_ENDIAN RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES | NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES | @@ -332,7 +333,8 @@ static void nouveau_nv40_context_init(drm_device_t *dev, */ RAMFC_WR(DMA_PUT , init->put_base); RAMFC_WR(DMA_GET , init->put_base); - RAMFC_WR(DMA_INSTANCE , cb_obj->instance >> 4); + RAMFC_WR(DMA_INSTANCE , nouveau_chip_instance_get(dev, + cb_obj->instance)); RAMFC_WR(DMA_FETCH , 0x30086078); RAMFC_WR(DMA_SUBROUTINE, init->put_base); RAMFC_WR(GRCTX_INSTANCE, 0); /* XXX */ @@ -471,7 +473,8 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, NV_WRITE(NV_PFIFO_CACH1_DMAP, init->put_base); NV_WRITE(NV_PFIFO_CACH1_DMAG, init->put_base); - NV_WRITE(NV_PFIFO_CACH1_DMAI, cb_obj->instance >> 4); + NV_WRITE(NV_PFIFO_CACH1_DMAI, + nouveau_chip_instance_get(dev, cb_obj->instance)); NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF); NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF); |