| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2007-03-26 | nouveau: move card initialisation into the drm | Ben Skeggs | |
| The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E | |||
| 2007-03-23 | nouveau: rework nouveau_fifo_alloc() so the drm can create internal FIFOs | Ben Skeggs | |
| 2007-03-23 | nouveau: remove unused cruft | Ben Skeggs | |
| 2007-03-21 | nouveau: support multiple channels per client (breaks drm interface) | Ben Skeggs | |
| 2007-03-13 | nouveau: make sure cmdbuf object gets destroyed | Ben Skeggs | |
| 2007-03-13 | nouveau: associate all created objects with a channel + cleanups | Ben Skeggs | |
| 2007-03-11 | nouveau: PUT,GET, not 2xPUT | Patrice Mandin | |
| 2007-02-28 | nouveau: intrusive drm interface changes | Ben Skeggs | |
| graphics objects: - No longer takes flags/dmaobj parameters, requires some major changes to the ddx to setup the object through the FIFO. This change is likely to cause breakages on some cards (tested on NV05,NV28,NV35, NV40 and NV4E). dma objects: - now takes a "class" parameter, not really used yet but we may need it at some point. - parameters are checked, so clients can't randomly create DMA objects pointing at whatever they feel like. misc: - Added FB_SIZE/AGP_SIZE getparams - Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR - Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't NOTIFICATION_PENDING. | |||
| 2007-02-14 | nouveau: fix the build on big endian (thanks CyberFoxx) | Stephane Marchesin | |
| 2007-02-06 | nouveau: more work on the nv04 context switch code. | Stephane Marchesin | |
| 2007-02-03 | nouveau: and of course, I was missing the last nv04 piece. | Stephane Marchesin | |
| 2007-02-03 | nouveau: rename registers to their proper names. | Stephane Marchesin | |
| 2007-01-25 | nouveau: simplify and fix BIG_ENDIAN flags | Patrice Mandin | |
| 2007-01-18 | nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH switching. | Jeremy Kolb | |
| 2007-01-17 | nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet. | Jeremy Kolb | |
| Hook into nv20 pgraph switching functions (they're identical for nv3x). Actually call nv30_pgraph_context_init so the ctx_table is allocated. Thanks to Carlos Martin for the help. | |||
| 2007-01-13 | nouveau: nv20 graph ctx switch. | Matthieu Castet | |
| Untested... | |||
| 2007-01-13 | nouveau: first step to make graph ctx works | Matthieu Castet | |
| It is still not working, but now we could use some 3D commands without needed to run nvidia blob before. | |||
| 2007-01-12 | nouveau : remove useless init : we clear RAMIN before | Matthieu Castet | |
| 2007-01-12 | nouveau: get nv30 context switching to work. | Jeremy Kolb | |
| * Pulled in some registers from nv10reg.h. Needed for context switching. * Filled in nv30 graphics context (based on nv40_graph.c). * Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work. | |||
| 2007-01-08 | nouveau: avoid allocating vram that's used as instance memory. | Ben Skeggs | |
| 2007-01-05 | Merge branch 'master' of git+ssh://matc@git.freedesktop.org/git/mesa/drm/ | Matthieu Castet | |
| 2007-01-05 | Add basic pgraph context for nv10. | Matthieu Castet | |
| It only fake a context switch : pgraph state are not save/restored. | |||
| 2007-01-05 | Cleanup the nv04 fifo code a bit. | Stephane Marchesin | |
| 2007-01-02 | nouveau: oops, forgot to free RAMIN.. | Ben Skeggs | |
| 2007-01-02 | nouveau: Hook up grctx code for NV4x. | Ben Skeggs | |
| This is enough to get grctx switching going on my NV40 and C51 after the binary driver has initialised the card first. Bumping the drm patchlevel because the ddx needs some modifications to have NV4x work at all with these changes. | |||
| 2007-01-02 | nouveau: Only clobber PFIFO if no channels are already alloc'd | Ben Skeggs | |
| With this change the GPU is responsible for doing the channel switch itself. This is needed for the upcoming NV4x PGRAPH context work as we don't yet know enough to manually swap PGRAPH contexts. | |||
| 2006-12-26 | nouveau: Alloc cmdbuf for each channel individually | Ben Skeggs | |
| 2006-12-21 | nouveau: save/restore endianness flag on FIFO switch | Ben Skeggs | |
| This makes my G5 survive glxinfo and nouveau_demo - airlied | |||
| 2006-12-12 | Port remaining NV4 RAMIN access from the ddx into the drm. | Ben Skeggs | |
| Should fix lockups seen on NV4 cards. | |||
| 2006-12-03 | Merge the pciid work. | Stephane Marchesin | |
| Add getparams for AGP and FB physical adresses. Fix the MEM_ALLOC issue properly. Fix context switches for nv44. Change the DRM version to 0.0.1. | |||
| 2006-11-30 | Use nouveau_mem.c to allocate RAMIN. | Ben Skeggs | |
| 2006-11-30 | Wrap access to objects in RAMIN. | Ben Skeggs | |
| This will make it easier to support extra RAMIN in vram at a later point. | |||
| 2006-11-28 | For nv10, bit 16 of RAMFC need to be set for 64 bytes fifo context. | Matthieu Castet | |
| When cleaning a fifo, we shouldn't assume everybody use nv40 ;) Fill DMA_SUBROUTINE fill correct value. | |||
| 2006-11-18 | Only return FIFO number if the FIFO is marked as in use.. | Ben Skeggs | |
| 2006-11-18 | Check some return vals, fixes a couple of oopses. | Ben Skeggs | |
| 2006-11-17 | Dump some useful info when a PGRAPH error occurs. | Ben Skeggs | |
| The "channel" detect doesn't work on my nv40, but the rest seems to produce sane info. | |||
| 2006-11-14 | Completely untested NV10/20/30 FIFO context switching changes. | Ben Skeggs | |
| 2006-11-14 | Restructure initialisation a bit. | Ben Skeggs | |
| - Do important card init in firstopen - Give each channel it's own cmdbuf dma object - Move RAMHT config state to the same place as RAMRO/RAMFC - Make sure instance mem for objects is *after* RAM{FC,HT,RO} | |||
| 2006-11-14 | Hack around yet another "X restart borkage without nouveau.ko reload" problem. | Ben Skeggs | |
| On X init, PFIFO and PGRAPH are reset to defaults. This causes the GPU to loose the configuration done by the drm. Perhaps a CARD_INIT ioctl a proper solution to having this problem again in the future.. | |||
| 2006-11-06 | fixup fifo size so it is page aligned | Dave Airlie | |
| 2006-10-18 | Remove hack which delays activation of a additional channel. The previously ↵ | Ben Skeggs | |
| active channel's state is saved to RAMFC before PFIFO gets clobbered. | |||
| 2006-10-17 | NV40: *Now* fifo ctx switching works for me.. | Ben Skeggs | |
| Ok, I lied before.. it was a fluke it worked and required magic to repeat it.. It actually helps to fill in RAMFC entries in the correct place. The code also clears RAMIN entirely instead of just the hash-table. | |||
| 2006-10-17 | NV40: FIFO context switching now WorksForMe(tm) | Ben Skeggs | |
| 2006-10-17 | Setup NV40 RAMFC (in wrong location.. but anyway), rearrange the RAMFC setup ↵ | Ben Skeggs | |
| code a bit. | |||
| 2006-10-14 | Again more work on context switches. They work, sometimes. And when they do ↵ | Stephane Marchesin | |
| they seem to screw up the PGRAPH state. | |||
| 2006-10-14 | Add the missing breaks. | Stephane Marchesin | |
| 2006-10-13 | Fix the fifo context size on nv10, nv20 and nv30. | Stephane Marchesin | |
| 2006-10-14 | Fix some randomness in activating a second channel on NV40 (odd GET/PUT ↵ | Ben Skeggs | |
| vals). Ch 1 GET now advances, but no ctx_switch. | |||
| 2006-10-12 | Still more work on the context switching code. | Stephane Marchesin | |
| 2006-10-12 | More work on the context switch code. Still doesn't work. I'm mostly ↵ | Stephane Marchesin | |
| convinced it's an initialization issue. | |||
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index : renesas/drm.git | |
| libdrm, cloned from git://anongit.freedesktop.org/mesa/drm | Laurent Pinchart |
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