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2008-10-09i915: Cleanup interrupt handlingRobert Noland
2008-08-24i915: Fix i915 build on FreeBSDRobert Noland
ifdef out all the gem stuff for now. Also, the msi stuff isn't portable the way it is... I'll try and fix that up sometime soon.
2008-08-24i915: Convert vblank on disabled pipe DRM_ERROR to DRM_DEBUG.Robert Noland
2008-08-24i915: Move spinlock init / destroy to load / unload time.Robert Noland
This resolves the panic on FreeBSD during VT switch, without attempting any of the more lofty goals for the time being.
2008-08-08Merge branch 'drm-gem'Eric Anholt
Conflicts: shared-core/i915_dma.c This brings in kernel support and userland interface for intel GEM.
2008-08-01Revert "i915: Move all of the irq install/uninstall to load time."Dave Airlie
This reverts commit 965a72202b439068e62ac341990f51953457b202. Please re-do over properly
2008-07-30i915: more version checksDave Airlie
2008-07-28Merge commit 'origin/master' into drm-gemEric Anholt
Conflicts: linux-core/Makefile.kernel shared-core/i915_dma.c shared-core/i915_drv.h shared-core/i915_irq.c
2008-07-23i915: Move all of the irq install/uninstall to load time.Robert Noland
This resolves a panic on FreeBSD which was caused by trying to re-initialize the swap lock. It's just much easier to initialize all of the locks at load time. It should also ensure that the vblank structures are available earlier.
2008-07-19i915: convert to using drm_vblank_get/put around vblank counter usageJesse Barnes
All interrupt off vblank count updates are done in drm_vblank_get/put now, so convert users of the vblank counter over to that interface.
2008-07-17i915: remove old broken vblank codeJesse Barnes
Remove the unused (and broken) "in vblank" code now that the core has been fixed to use a counter while interrupts are enabled. Also make the vblank pipe get/set ioctls into dumb stub functions, since with the new code we can no longer let userspace control whether vblank interrupts are enabled, or the core code will misbehave.
2008-07-15This is a modified version of Hong's patch from last month, with a fewHong Liu
modifications to make it work correctly on my test hardware (altered the backlight write function, made it enable the legacy backlight controller interrupts on mobile hardware, sorted the interrupt function so we don't get an excessive number of vblank interrupts). This lets the backlight keys on my T61 work properly, though there's a 750msec or so delay between the request and the brightness actually changing - this sounds awfully like the hardware spinning waiting for a status flag to become ready, but as far as I can tell they're all set correctly. If anyone can figure out what's wrong here, it'd be nice to know. Some of the functions are still stubs and just tell the hardware that the request was successful. These can be filled in as kernel modesetting gets integrated. I think it's worth getting this in anyway, since it's required for backlight control to work properly on some new platforms. Signed-off-by: Matthew Garrett <mjg@redhat.com>
2008-07-01i915: only use tiled blits on 965+Jesse Barnes
When scheduled swaps occur, we need to blit between front & back buffers. I the buffers are tiled, we need to set the appropriate XY_SRC_COPY tile bit, only on 965 chips, since it will cause corruption on pre-965 (e.g. 945). Bug reported by and fix tested by Tomas Janousek <tomi@nomi.cz>. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-06-24[intel] Get vblank pipe from irq_mask_reg instead of hardware enable regKeith Packard
With the interrupt enable/disable using only the mask register, it was wrong to use the enable register to detect which pipes had vblank detection turned on. Also, as we keep a local copy of the mask register around, and MSI machines smack the hardware during the interrupt handler, it is more efficient and more correct to use the local copy.
2008-06-24[intel] Create functions to enable/disable interruptsKeith Packard
This shares common code sequences for managing the interrupt register bits
2008-06-24i915: register definition & header file cleanupJesse Barnes
It would be nice if one day the DRM driver was the canonical source for register definitions and core macros. To that end, this patch cleans things up quite a bit, removing redundant definitions (some with different names referring to the same register) and generally tidying up the header file.
2008-06-21[intel] Use IMR instead of IER to pend interrupts during ISRKeith Packard
Noting that the interrupt mask register was more reliable than the interrupt enable register for managing interrupts in user_irq_on/user_irq_off, this patch replaces the remaining IER frobbing with IMR instead. The test which exposes IER related failures is: $ glxgears & glxgears & glxgears (reposition the glxgears windows away from the upper left corner) $ while :; do x11perf -rect100 -reps 800 -repeat 1; sleep 1; done & $ while :; do runoa; runet; done &
2008-06-21[intel] Count received interruptsKeith Packard
Another patch adds this to a /proc/dri file for debugging and monitoring.
2008-06-20[intel-gem] Add intel-specific /proc entries to help monitor gem operationKeith Packard
This adds gem_active, gem_flushing, gem_inactive, gem_request and gem_seqno entries to monitor gem operation and help debug issues.
2008-06-13[intel] Enable MSI for i915 IRQKeith Packard
2008-06-13[intel] Restructure irq to pend all work until after iir write.Keith Packard
The interrupt identity register must be writen before any work occurs lest we drop an interrupt on the floor. This patch just shuffles code around to make sure that IIR is written as early as possible.
2008-06-13Fix i915_wait_irq in the presence of interrupt masking.Eric Anholt
In the short-circuit code for the breadcrumb already being new enough, we need to update the sarea_priv copy of the breadcrumb just as if we had waited. Otherwise userland error checking will notice that we returned too early based on its wrong information, and call wait_irq again (leading to spinning until someone else comes along and updates the sarea_priv). This bug was hidden when we had interrupt masking disabled, such as in master, since the interrupt handler would update sarea_priv.
2008-06-13[gem] Remove the interrupt handler for retiring requests.Eric Anholt
This was insufficient once we started masking interrupts to only when someone was waiting for them (and would thus retire requests themselves). It was replaced by the retire_timer.
2008-06-12Don't clear USER_INTERRUPT if we're not handling it.Eric Anholt
This fixes a regression from commit d434b64f6a760d85295e32298a9a1f3624ee1b69 which could cause us to fail to wake up for user interrupts if we lost a race.
2008-06-10[intel] Fix BUG_ON trigger in irq masking if you did on/off with irqs disabled.Eric Anholt
2008-06-10[gem] Manage the ringbuffer from the kernel in the GEM case.Eric Anholt
This requires that the X Server use the execbuf interface for buffer submission, as it no longer has direct access to the ring. This is therefore a flag day for the gem interface. This also adds enter/leavevt ioctls for use by the X Server. These would get stubbed out in a modesetting implementation, but are required while in an environment where the device's state is only managed by the DRM while X has the VT.
2008-05-30Merge commit 'origin/master' into drm-gemEric Anholt
Conflicts: linux-core/Makefile.kernel shared-core/i915_drv.h shared-core/nouveau_state.c
2008-05-27[FreeBSD] Add vblank-rework support and get drivers building.Robert Noland
The i915 driver now works again.
2008-05-26[i915] leave interrupts masked off when not in use.Keith Packard
The interrupt enable register cannot be used to temporarily disable interrupts, instead use the interrupt mask register. Note that this change means that a pile of buffers will be left stuck on the chip as the final interrupts will not be recognized to come and drain things.
2008-05-22[gem] Release GEM buffers from work task scheduled from IRQ.Eric Anholt
There are now 3 lists. Active is buffers currently in the ringbuffer. Flushing is not in the ringbuffer, but needs a flush before unbinding. Inactive is as before. This prevents object_free → unbind → wait_rendering → object_reference and a kernel oops about weird refcounting. This also avoids an synchronous extra flush and wait when freeing a buffer which had a write_domain set (such as a temporary rendered to and then from using the 2d engine). It will sit around on the flushing list until the appropriate flush gets emitted, or we need the GTT space for another operation.
2008-05-06GEM: Use irq-based fencing rather than syncing and evicting every exec.Eric Anholt
2008-04-20[I915] Handle tiled buffers in vblank taskletKeith Packard
The vblank tasklet update code must build 2D blt commands with the appropriate tiled flags.
2008-04-20On I965, use correct 3DSTATE_DRAWING_RECTANGLE command in vblankKeith Packard
The batchbuffer submission paths were fixed to use the 965-specific command, but the vblank tasklet was not. When the older version is sent, the 965 will lock up.
2008-03-08Switch from PIPE_VBLANK to PIPE_EVENT interrupts.Keith Packard
My 965GM gets interrupts stuck when using the old PIPE_VBLANK interrupt. Switch to the PIPE_EVENT interrupt mechanism, and set the PIPE*STAT registers to use START_VBLANK on 965 and VBLANK on previous chips.
2008-03-03 [i915] 2D driver may reset Frame count value, this may lead driverZou Nan hai
to leap it's vblank count a huge value. This will stall some applications that switch video mode if vblank_mode is set to a non zero value in drirc.
2008-02-13i915: Make sarea_priv setup optional.Kristian Høgsberg
2008-01-24Remove broken 'in vblank' accountingJesse Barnes
We need to return an accurate vblank count to the callers of ->get_vblank_counter, and in the Intel case the actual frame count register isn't udpated until the next active line is displayed, so we need to return one more than the frame count register if we're currently in a vblank period. However, none of the various ways of doing this is working yet, so disable the logic for now. This may result in a few missed events, but should fix the hangs some people have seen due to the current code tripping the wraparound logic in drm_update_vblank_count.
2008-01-23Fix thinko in get_vblank_counterJesse Barnes
Should use vtotal not htotal to figure out if we're in a vblank period.
2008-01-22Correct vblank count valueJesse Barnes
The frame count registers don't increment until the start of the next frame, so make sure we return an incremented count if called during the actual vblank period.
2008-01-22i915 irq fixesJesse Barnes
Ack the IRQs correctly (PIPExSTAT first followed by IIR). Don't read vblank counter registers on disabled pipes (might hang otherwise). And deal with flipped pipe/plane mappings if present.
2008-01-22Merge branch 'master' into vblank-rework, including mach64 supportJesse Barnes
Conflicts: linux-core/drmP.h linux-core/drm_drv.c shared-core/i915_drv.h shared-core/i915_irq.c shared-core/mga_irq.c shared-core/radeon_irq.c shared-core/via_irq.c Mostly trivial conflicts. mach64 support from Mathieu Bérard.
2008-01-22Revert "Fix pipe<->plane mapping vs. vblank handling (again)"Dave Airlie
This reverts commit bfc29606e4a818897eebca46a5e23bbe7bc3ce25. This regresses i915 here for me I can't get greater than 0.333 fps with gears
2008-01-03drm: cleanup DRM_DEBUG() parametersMárton Németh
As DRM_DEBUG macro already prints out the __FUNCTION__ string (see drivers/char/drm/drmP.h), it is not worth doing this again. At some other places the ending "\n" was added. airlied:- I cleaned up a few that this patch missed also
2007-12-17drm: don't cast a pointer to pointer of list_headLi Zefan
The casting is safe only when the list_head member is the first member of the structure.
2007-12-07Fix pipe<->plane mapping vs. vblank handling (again)Jesse Barnes
If drmMinor >= 6, the intel DDX driver will enable vblank events on both pipes. If drmMinor >= 10 on pre-965 chipsets, the intel DDX driver will swap the pipe<->plane mapping to allow for framebuffer compression on laptop screens. This means the secondary vblank counter (corresponding to pipe B) will be incremented when vblank interrupts occur. Now Mesa waits for vblank events on whichever plane has a greater portion of the displayed window. So it will happly ask to wait for the primary counter even though that one won't increment. So we can fix this in either the DDX driver, Mesa or the kernel (though I thought we already had several times). Since current (and previous) userspace assumes it's talking about a pipe == plane situation and now uses planes when talking to the kernel, we should probably just hide the mapping details there (indeed they already are hidden there for vblank swaps), which this patch does. So as far as userland is concerned, whether we call things planes or pipes is irrelevant, as long as kernel developers understand that userland hands them planes and they have to figure out which pipe that corresponds to (which will typically be the same on 965+ hardware and reversed on pre-965 mobile chips).
2007-12-05Remove references to the sarea_priv perf_boxes field.Kristian Høgsberg
This field isn't touched or read by any other code in the stack so it's time to retire these last few references.
2007-11-06i915: cleanup most of the whitespaceDave Airlie
2007-11-05drm: remove lots of spurious whitespace.Dave Airlie
Kernel "cleanfile" script run.
2007-10-30Merge branch 'master' into vblank-rework, fixup remaining driversJesse Barnes
Conflicts: linux-core/drmP.h linux-core/drm_drv.c linux-core/drm_irq.c shared-core/i915_drv.h shared-core/i915_irq.c shared-core/mga_drv.h shared-core/mga_irq.c shared-core/radeon_drv.h shared-core/radeon_irq.c Merge in the latest master bits and update the remaining drivers (except mach64 which math_b is working on). Also remove the 9xx hack from the i915 driver; it seems to be correct.
2007-10-14i915: fix vbl_swap allocationDave Airlie