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2014-04-29intel/chv: Add Cherryview PCI IDsVille Syrjälä
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2014-04-17intel: Fix some format stringsThierry Reding
Some of the format strings for debug messages use the wrong modifier to print sizes. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-04-17Mark functions printf-like where possibleThierry Reding
These functions all take a format string and either a list of variable arguments or a va_list. Use the new DRM_PRINTFLIKE macro to tell the compiler about it so that the arguments can be checked against the format string. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-01-20intel: Create a new drm_intel_bo offset64 field.Kenneth Graunke
The existing 'offset' field is unfortunately typed as 'unsigned long', which is unfortunately only 4 bytes with a 32-bit userspace. Traditionally, the hardware has only supported 32-bit virtual addresses, so even though the kernel uses a __u64, the value would always fit. However, Broadwell supports 48-bit addressing. So with a 64-bit kernel, the card virtual address may be too large to fit in the 'offset' field. Ideally, we would change the type of 'offset' to be a uint64_t---but this would break the libdrm ABI. Instead, we create a new 'offset64' field to hold the full 64-bit value from the kernel, and store the 32-bit truncation in the existing 'offset' field, for compatibility. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-01-20intel: Track whether a buffer is idle to avoid trips to the kernel.Eric Anholt
I've seen a number of apps spending unreasonable amounts of time in drm_intel_bo_busy during the buffer mapping process. We can't track idleness in general, in the case of buffers shared across processes. But this should significantly reduce our overhead for checking for busy on things like VBOs. Improves (unoptimized) glamor x11perf -f8text by 0.243334% +/- 0.161498% (n=1549), which has formerly been spending about .5% of its time hitting the kernel for drm_intel_gem_bo_busy(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-01-10intel: Handle malloc fails in context createBen Widawsky
The previous code would just use the potentially unallocated variable, which is probably okay most of the time, but not very nice to the user of the library. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2014-01-10intel: squash unused variable 'bo_gem'Ben Widawsky
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-12-13intel/test_decode: Allow gen8 to be infered from the batch filenamesDamien Lespiau
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-11-26 intel: Track known prime buffers for re-useKeith Packard
If the application sends us a file descriptor pointing at a prime buffer that we've already got, we have to re-use the same bo_gem structure or chaos will result. Track the set of all known prime objects and look to see if the kernel has returned one of those for a new file descriptor. Also checks for prime buffers in the flink case. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-20intel: Use memset instead of VG_CLEARIan Romanick
The ioctl expects that certain fields will be zeroed, so we should allow the helper function to actually work in non-Valgrind builds. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reported-by: Zhenyu Wang <zhenyuw@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-15intel: Add support for GPU reset status query ioctlIan Romanick
I would have just used the drmIoctl interface directly in Mesa, but the ioctl needs some data from the drm_intel_context that is not exposed outside libdrm. This ioctl is in the drm-intel-next tree as b635991. v2: Update based on Mika's kernel work. v3: Fix compile failures from last-minute typos. Sigh. v4: Import the actual changes from the kernel i915_drm.h. Only comments on some fields of drm_i915_reset_stats differed. There are still some deltas between the kernel i915_drm.h and the one in libdrm, but those can be resolved in other patches. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v3] Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-08Revert "intel: Add support for GPU reset status query ioctl"Dave Airlie
This reverts commit 6335e1d28c422050024bcf4100c4fb3a5bac2afb. No taxation without representation, in other words no userspace without kernel stuff being in a stable location, either drm-next but I'll accept drm-intel-next for intel specific stuff.
2013-11-07intel: Add support for GPU reset status query ioctlIan Romanick
I would have just used the drmIoctl interface directly in Mesa, but the ioctl needs some data from the drm_intel_context that is not exposed outside libdrm. v2: Update based on Mika's kernel work. v3: Fix compile failures from last-minute typos. Sigh. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-07intel/bdw: Update MI_BATCH_BUFFER_START for aub dumpsDamien Lespiau
The command now takes a 48bits address and is thus 1 dword longer. v2 (Ben): commit message: s/byte/dword (Eric) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07intel/bdw/aub: Update AUB trace block writes for 48-bit addressing.Kenneth Graunke
Since our aub file dumping's GTT handling is totally fake, we always put everything in the low 4GB anyway and shouldn't ever need to set AddressHigh to anything other than 0. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> [ben: slight commit message change] Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07intel/bdw: Add gen8 to the decode initDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07intel/bdw: Handle gen8 bufmgr_initBen Widawsky
[bwidawsk: Added Damien's SOB] Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07intel/bdw: Add broadwell chipset IDsBen Widawsky
v2: Rename s/<SECRET>/IRIS/ Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-10-29intel: Add MI_LOAD_REGISTER_MEM to intel_decode.c.Kenneth Graunke
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-10-29intel: Add the Gen6+ version of MI_REPORT_PERF_COUNT to intel_decode.c.Kenneth Graunke
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-10-10intel: Set bo size from lseek if kernel supports itKristian Høgsberg
The various create and open functions set the buffer size, but drm_intel_bo_gem_create_from_prime() is an exception. In the 3.12 kernel we can now use lseek on the prime fd to determine the size of the bo. Use that and override the userprovided size. If the kernel doesn't support this, we get an error and fall back to the user provided size. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2013-08-30intel: Update package name and description in libdrm_intel.pcEmil Velikov
Currently the package name and description duplicate that of the core libdrm. Update those to reflect reality. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
2013-07-16intel: silence valgrind warnings for unsynchronized mapsChia-I Wu
Mark the address ranges as accessible with VALGRIND_MAKE_MEM_DEFINED. Signed-off-by: Chia-I Wu <olvaffe@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-06-10intel/aub: Implement a way to specify the output .aub filenameDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-10intel/aub: Return early if we disable aub dumpsDamien Lespiau
No need to prepare the .aub header and dump in that case, it'll be done with the next call with true. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-10intel/aub: Sync the AUB defines with mesa'sDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-05intel: Adding more reserved PCI IDs for Haswell.Rodrigo Vivi
At DDX commit Chris mentioned the tendency we have of finding out more PCI IDs only when users report. So Let's add all new reserved Haswell IDs. Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701 Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-05intel: Fix Haswell GT3 names.Rodrigo Vivi
When publishing first HSW ids we weren't allowed to use "GT3" codname. But this is the correct codname and Mesa is using it already. So to avoid people getting confused why in Mesa it is called GT3 and here it is called GT2_PLUS let's fix this name in a standard and correct way. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by: Chad Versace <chad.versace@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-04-27intel: Add support for VEBOX ring (v2)Xiang, Haihao
v2: Fix the test for has_vebox Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-04-04intel-decode: Fix gen6 HIER_DEPTH_BUFFER decodingDaniel Vetter
It accidentally used the cmd id for the gen7 command and had an outdated lenght field. Spotted while trying to make sense of an ivb error_state from mesa 7.11 ... Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-03-28intel: Fix Haswell CRW PCI IDs.Kenneth Graunke
The second digit was off by one, which meant we accidentally treated GT(n) as GT(n-1). This also meant no support for GT1 at all. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-27intel_chipset: Fix up VLV confusionVille Syrjälä
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2013-03-27intel_chipset: Use parens around macro argumentsVille Syrjälä
Protect the macro argument evaluations with parens. This is already touching most lines, so while at it, fix up all white space to uniform style throughout the file. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2013-02-11intel_chipset: Merge intel-gpu-tools chipsetsBen Widawsky
Intel GPU Tools is newer and arguably better. This change doesn't completely merge the files because it's a bit simpler if we move the I9XX macro over to Intel GPU Tools, and don't move over a few macros from IGT that libdrm doesn't care about. It has been discussed, and would seem even easier if Intel GPU Tools simply used the libdrm header files. Whether or not we move to that, this should help that effort. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2013-02-06intel: fix length mask for Gen5/Gen6 3DSTATE_CLEAR_PARAMSChris Forbes
On Gen6, bit 15 is now `Depth Clear Value Valid`. This was being treated as part of the length, and failing the rest of the batchbuffer decode. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2013-02-06intel/aub: Actually run BLT batches on the blit ring.Kenneth Graunke
We didn't set the ring flag for BLT batches, so they got run on the render ring. Shenanigans ensued, especially when we sent commands that were only valid on the BLT ring. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-02-02intel: add more VLV PCI IDsJesse Barnes
2013-01-13intel: Remove the fence count contributions when clearing relocsChris Wilson
As we clear the relocs from the bo, we also need to clear the contribution of the reloc_target_bo from the fence count. Otherwise they are leaked and prevent any further relocations being added to the bo.
2012-11-10intel: Fix missing ETIME on BSD operating systemsDavid Shao
Originally posted to Free Desktop bug #52549 by David Shao. Resolves Gentoo Bug #433403. Commit message by Richard Yao. Reviewed-by: Richard Yao <ryao@gentoo.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> References: https://bugs.freedesktop.org/show_bug.cgi?id=52549 Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2012-10-07intel: Silence a trivial compiler warningChris Wilson
intel_bufmgr_gem.c: In function 'drm_intel_bo_gem_export_to_prime': intel_bufmgr_gem.c:2477:6: warning: unused variable 'ret' [-Wunused-variable] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-10-07intel: Correct the word decoding for gen2 3DSTATE_LOAD_STATE_IMMEDIATE_1Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-10-07intel: Fix "properly test for HAS_LLC"Chris Wilson
commit 92fd0ce4f659d7b0680543e9e5b96a3c7737a5f3 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Fri Aug 31 11:16:53 2012 +0200 intel: properly test for HAS_LLC missed slightly and in effect had no effect on the outcome of checking whether the kernel/chipset supported LLC. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-09-14intel: Mark bo's exported to prime as not reusableKristian Høgsberg
It's the same situation as flink and we need take the same precautions. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2012-09-13intel: add support for ValleyViewJesse Barnes
Just some PCI ID stuff to enable the right features.
2012-09-01intel: properly test for HAS_LLCDaniel Vetter
If the kernel supports the test, we need to check the param. Copy&pasta from the above checks that only look at the return value. Interesting how much one can get such a simple interface wrong. Issue created in commit 151cdcfe685ee280a4344dfc40e6087d74a5590f Author: Eugeni Dodonov <eugeni.dodonov@intel.com> Date: Tue Jan 17 15:20:19 2012 -0200 intel: query for LLC support Patch even claims to have fixed this in v2, but is actually unchanged from v1. Reported-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-12intel: Use VG_CLEAR on the context destroy ioctl as well.Kenneth Graunke
Otherwise pad appears uninitialized and valgrind grumbles. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-08-10intel: Add a function for the new register read ioctl.Eric Anholt
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2012-08-08intel: add more Haswell PCI IDsPaulo Zanoni
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
2012-08-08intel: Bail gracefully if we encounter an unknown Intel deviceChris Wilson
Otherwise we end up with X hitting a fail-loop as the embedded libGL stacks asserts whilst initialising. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-02intel: Quiet valgrind warnings in context creation.Eric Anholt
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 12:09:34 +0000