summaryrefslogtreecommitdiff
path: root/intel/intel_chipset.h
AgeCommit message (Collapse)Author
2015-05-18intel: Add the Broxton PCI IDsDamien Lespiau
Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-09-30intel/skl: Add SKL PCI idsDamien Lespiau
v2: Add more PCI IDs (Michael H. Nguyen) v3: Synchronize one more with the kernel PCI IDs (Damien) Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Michael H. Nguyen <michael.h.nguyen@intel.com>
2014-04-29intel/chv: Add Cherryview PCI IDsVille Syrjälä
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2013-11-07intel/bdw: Add broadwell chipset IDsBen Widawsky
v2: Rename s/<SECRET>/IRIS/ Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-06-05intel: Adding more reserved PCI IDs for Haswell.Rodrigo Vivi
At DDX commit Chris mentioned the tendency we have of finding out more PCI IDs only when users report. So Let's add all new reserved Haswell IDs. Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701 Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-05intel: Fix Haswell GT3 names.Rodrigo Vivi
When publishing first HSW ids we weren't allowed to use "GT3" codname. But this is the correct codname and Mesa is using it already. So to avoid people getting confused why in Mesa it is called GT3 and here it is called GT2_PLUS let's fix this name in a standard and correct way. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by: Chad Versace <chad.versace@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-28intel: Fix Haswell CRW PCI IDs.Kenneth Graunke
The second digit was off by one, which meant we accidentally treated GT(n) as GT(n-1). This also meant no support for GT1 at all. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-27intel_chipset: Fix up VLV confusionVille Syrjälä
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2013-03-27intel_chipset: Use parens around macro argumentsVille Syrjälä
Protect the macro argument evaluations with parens. This is already touching most lines, so while at it, fix up all white space to uniform style throughout the file. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2013-02-11intel_chipset: Merge intel-gpu-tools chipsetsBen Widawsky
Intel GPU Tools is newer and arguably better. This change doesn't completely merge the files because it's a bit simpler if we move the I9XX macro over to Intel GPU Tools, and don't move over a few macros from IGT that libdrm doesn't care about. It has been discussed, and would seem even easier if Intel GPU Tools simply used the libdrm header files. Whether or not we move to that, this should help that effort. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2013-02-02intel: add more VLV PCI IDsJesse Barnes
2012-09-13intel: add support for ValleyViewJesse Barnes
Just some PCI ID stuff to enable the right features.
2012-08-08intel: add more Haswell PCI IDsPaulo Zanoni
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
2012-04-01intel: add Ivy Bridge GT2 server variantEugeni Dodonov
We were missing this one and it is being used by Bromolow. Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2012-03-22intel: Add some PCI IDs for Haswell.Kenneth Graunke
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2011-12-29intel: intel: Add IS_GEN[567] macros.Eric Anholt
These will be used by intel_decode.c, and were taken from intel-gpu-tools. Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2011-12-29intel: Make intel_chipset handle devid directly.Eric Anholt
This will make these macros reusable from intel_decode.c, which doesn't have a bufmgr_gem context, without faking the struct. We should generally only be using these macros from bufmgr_gem context setup anyway. Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
2010-03-02libdrm/intel: execbuf2 supportJesse Barnes
This patch to libdrm adds support for the new execbuf2 ioctl. If detected, it will be used instead of the old ioctl. By using the new drm_intel_bufmgr_gem_enable_fenced_relocs(), you can indicate that any time a fence register is actually required for a relocation target you will call drm_intel_bo_emit_reloc_fence instead of drm_intel_bo_emit_reloc, which will reduce fence register pressure. Signed-off-by: Eric Anholt <eric@anholt.net>
2010-02-25intel: Add initial support for Sandybridge, and clean up the #defines.Eric Anholt
2009-11-17Move libdrm/ up one levelKristian Høgsberg