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2008-03-29r300: Correctly translate the value for the R300_CMD_WAIT command.Oliver McFadden
Previously, the R300_CMD_WAIT command would write the passed directly to the hardware. However this is incorrect because the R300_WAIT_* values used are internal interface values that do not map directly to the hardware. The new function I have added translates the R300_WAIT_* values into appropriate values for the hardware before writing the register. Thanks to John Bridgman for pointing this out. :-)
2008-03-25nouveau: nv20 bios does not initialise PTIMERStuart Bennett
The wait functions depend on PTIMER, so write the old (incorrect, but working) values for uninitialised hw
2008-03-24i915: fix oops on agp=offDave Airlie
Kernel bug 10289.
2008-03-24Merge branch 'r500-fp'Dave Airlie
2008-03-24nouveau: silence warningBen Skeggs
2008-03-24nv40: voodoo - not quite.Ben Skeggs
2008-03-24nv40: allocate massive amount of PRAMIN for grctx on all chipsets.Ben Skeggs
More or less a workaround for issues on some chipsets where a context switch results in critical data in PRAMIN being overwritten by the GPU. The correct fix is known, but may take some time before it's a feasible option.
2008-03-21r500: fragment program upload is also used to upload constants.Dave Airlie
Limit frag address to 8 bits
2008-03-20drm: fixup r500fp submissionDave Airlie
2008-03-20nouveau: do not set on-board timer's numerator/denominator to bad valuesStuart Bennett
2008-03-19RADEON: switch over to new production microcodeAlex Deucher
This needs to be tested thoroughly before pushing to the kernel.
2008-03-19RADEON: production microcode for all radeons, r1xx-r6xxAlex Deucher
This updated microcode is not in use yet.
2008-03-19move some more r300 regs into not allowed on r500Dave Airlie
2008-03-18drm: add new rs690 pci idDave Airlie
2008-03-17Evict cached_mapped relocatee before applying reloc.Thomas Hellstrom
Fix that got left out after the intel-post-reloc merge.
2008-03-17initial r500 RS and FP register and upload codeDave Airlie
2008-03-17drm/pcigart: fix the pci gart to use the drm_pci wrapper.Dave Airlie
This is the correct fix for the RS690 and hopefully the dma coherent work. For now we limit everybody to a 32-bit DMA mask but it is possible for RS690 to use a 40-bit DMA mask for the GART table itself, and the PCIE cards can use 40-bits for the table entries. Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-03-16Avoid unnecessary waits for command regulator pause.Thomas Hellstrom
2008-03-16[via] Remove some leftover vars.Thomas Hellstrom
2008-03-16[via] Allow a little larger stride for SG DMA DownloadFromScreen.Thomas Hellstrom
2008-03-16[via] The millionth fixup for the millionth-1 attempt to stabilize the AGPThomas Hellstrom
DMA command submission. It's worth remembering that all new bright ideas on how to make this command reader work properly and according to docs will probably fail :( Bring in some old code.
2008-03-16[via] Fix driver after vblank-rework merge.Thomas Hellstrom
2008-03-16ati: fix rs690 igp gart by allocating the page table in 32-bit memoryDave Airlie
2008-03-16drm/rs690: set AGP_BASE_2 to 0Dave Airlie
2008-03-16drm: set rs690 gart base completly.Dave Airlie
The docs state bits 4-11 represent bits 32-39 of a 40-bit address
2008-03-16drm: this u32 should be a dma_addr_tDave Airlie
doesn't fix anything but just making it consistent
2008-03-14fix build problemsAlan Hourihane
2008-03-14drm: Fix race that can lockup the kernelMike Isely
The i915_vblank_swap() function schedules an automatic buffer swap upon receipt of the vertical sync interrupt. Such an operation is lengthy so it can't be allowed to happen in normal interrupt context, thus the DRM implements this by scheduling the work in a kernel softirq-scheduled tasklet. In order for the buffer swap to work safely, the DRM's central lock must be taken, via a call to drm_lock_take() located in drivers/char/drm/drm_irq.c within the function drm_locked_tasklet_func(). The lock-taking logic uses a non-interrupt-blocking spinlock to implement the manipulations needed to take the lock. This semantic would be safe if all attempts to use the spinlock only happen from process context. However this buffer swap happens from softirq context which is really a form of interrupt context. Thus we have an unsafe situation, in that drm_locked_tasklet_func() can block on a spinlock already taken by a thread in process context which will never get scheduled again because of the blocked softirq tasklet. This wedges the kernel hard. To trigger this bug, run a dual-head cloned mode configuration which uses the i915 drm, then execute an opengl application which synchronizes buffer swaps against the vertical sync interrupt. In my testing, a lockup always results after running anywhere from 5 minutes to an hour and a half. I believe dual-head is needed to really trigger the problem because then the vertical sync interrupt handling is no longer predictable (due to being interrupt-sourced from two different heads running at different speeds). This raises the probability of the tasklet trying to run while the userspace DRI is doing things to the GPU (and manipulating the DRM lock). The fix is to change the relevant spinlock semantics to be the interrupt-blocking form. After this change I am no longer able to trigger the lockup; the longest test run so far was 20 hours (test stopped after that point). Note: I have examined the places where this spinlock is being employed; all are reasonably short bounded sequences and should be suitable for interrupts being blocked without impacting overall kernel interrupt response latency. Signed-off-by: Mike Isely <isely@pobox.com>
2008-03-12Fix chip family for RV550Alex Deucher
2008-03-13nv50: force channel vram access through vmBen Skeggs
If we ever want to be able to use the 3D engine we have no choice. It appears that the tiling setup (required for 3D on G8x) is in the page tables. The immediate benefit of this change however is that it's now not possible for a client to use the GPU to render over the top of important engine setup tables, which also live in VRAM. G8x VRAM size is limited to 512MiB at the moment, as we use a 1-1 mapping of real vram pages to their offset within the start of a channel's VRAM DMA object and only populate a single PDE for VRAM use.
2008-03-12Merge branch 'intel-post-reloc'Thomas Hellstrom
Conflicts: linux-core/drm_compat.c linux-core/drm_compat.h linux-core/drm_ttm.c shared-core/i915_dma.c Bump driver minor to 13 due to introduction of new relocation type.
2008-03-12Bug # 14712Thomas Hellstrom
Disable page saving for GPU read-only TTMs.
2008-03-12Dont allow !sysadmin clients to alter the memory type ofThomas Hellstrom
NO_EVICT buffers.
2008-03-12Fix for debug memory routinesAlan Hourihane
2008-03-12Add error messageAlan Hourihane
2008-03-12Add an emergency pinnable memory quota for root-only processes.Thomas Hellstrom
2008-03-12Fix kernel crash when we hit OOM conditions.Thomas Hellstrom
(Alan Hourihane)
2008-03-12Avoid duplicate calls to drm_ttm_bind in some cases.Thomas Hellstrom
2008-03-12Make sure other TTM memory types than TT is really unbound when evicted.Thomas Hellstrom
2008-03-12Avoid large kmallocs.Thomas Hellstrom
2008-03-11nouveau: move AGP reset to mem_init_agpStuart Bennett
Also, power cycle PGRAPH when resetting AGP -- it seems to fix problems encountered by p0g on nv25
2008-03-10remove unneeded load callDave Airlie
2008-03-08Switch from PIPE_VBLANK to PIPE_EVENT interrupts.Keith Packard
My 965GM gets interrupts stuck when using the old PIPE_VBLANK interrupt. Switch to the PIPE_EVENT interrupt mechanism, and set the PIPE*STAT registers to use START_VBLANK on 965 and VBLANK on previous chips.
2008-03-08drm/radeon: check sarea_priv existsDave Airlie
2008-03-07nouveau: redo channel idle detectionBen Skeggs
Will hopefully work a bit better than previous code, which depended on knowing the channel's most recent PUT value. Some chips always return 0 on reading these regs, and currently userspace is the only other entity which knows the value.
2008-03-07nouveau: don't touch NV_USER regs on channel destroy.Ben Skeggs
Not only was this entirely pointless, it actually causes my NV30GL to die randomly when channels are destroyed.
2008-03-07flush_agp_mappings commitDave Airlie
2008-03-06drm/bo: allow non-suser priv to add kernel BOs.Dave Airlie
modprobe can be run with dropped capabilities we still want the kernel bos to work.
2008-03-05drm: Fix for non-coherent DMA PowerPCBenjamin Herrenschmidt
This patch fixes bits of the DRM so to make the radeon DRI work on non-cache coherent PCI DMA variants of the PowerPC processors. It moves the few places that needs change to wrappers to that other architectures with similar issues can easily add their own changes to those wrappers, at least until we have more useful generic kernel API. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2008-03-06ttm: make sure userspace can't destroy kernel create memory managersDave Airlie
this adds something to say the kernel initialised the memory region not the userspace. and blocks userspace from deallocating kernel areas