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authorStuart Bennett <sb476@cam.ac.uk>2008-03-25 18:30:05 +0000
committerStuart Bennett <sb476@cam.ac.uk>2008-03-25 18:32:26 +0000
commita81d07f64d7557da3c4888867a20d2eec94b4ec1 (patch)
treec0837c016d09745a9e57ed1238ed163ead178450
parentb0817a42e789a83454e6acba0578116829e2bf51 (diff)
nouveau: nv20 bios does not initialise PTIMER
The wait functions depend on PTIMER, so write the old (incorrect, but working) values for uninitialised hw
-rw-r--r--shared-core/nv04_timer.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/shared-core/nv04_timer.c b/shared-core/nv04_timer.c
index fbf185b4..616f197b 100644
--- a/shared-core/nv04_timer.c
+++ b/shared-core/nv04_timer.c
@@ -11,15 +11,17 @@ nv04_timer_init(struct drm_device *dev)
NV_WRITE(NV04_PTIMER_INTR_EN_0, 0x00000000);
NV_WRITE(NV04_PTIMER_INTR_0, 0xFFFFFFFF);
- /* Just use the pre-existing values for now; these regs are not written
- * in nv (driver writer missed a /4 on the address), and writing 8 and 3
- * to the correct regs breaks the timings on the LVDS hardware
- * sequencing microcode.
+ /* Just use the pre-existing values when possible for now; these regs
+ * are not written in nv (driver writer missed a /4 on the address), and
+ * writing 8 and 3 to the correct regs breaks the timings on the LVDS
+ * hardware sequencing microcode.
* A correct solution (involving calculations with the GPU PLL) can
* be done when kernel modesetting lands
- NV_WRITE(NV04_PTIMER_NUMERATOR, 0x00000008);
- NV_WRITE(NV04_PTIMER_DENOMINATOR, 0x00000003);
*/
+ if (!NV_READ(NV04_PTIMER_NUMERATOR) || !NV_READ(NV04_PTIMER_DENOMINATOR)) {
+ NV_WRITE(NV04_PTIMER_NUMERATOR, 0x00000008);
+ NV_WRITE(NV04_PTIMER_DENOMINATOR, 0x00000003);
+ }
return 0;
}