| Age | Commit message (Collapse) | Author |
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nouveau-1
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they seem to screw up the PGRAPH state.
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vals). Ch 1 GET now advances, but no ctx_switch.
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convinced it's an initialization issue.
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Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet).
Removed the PFIFO_REINIT ioctl. I hope it's that a good idea...
Requires the upcoming commit to the DDX.
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r100/r200 as others might be unsafe (r300 already does this), and add checking for these we need but aren't safe. Check the RADEON_CP_INDX_BUFFER packet on both r200 and r300 as it isn't safe neither.
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mach64_state.c: convert the DRM_MACH64_BLIT ioctl to submit a pointer to
user-space memory rather than a DMA buffer index, similar to DRM_MACH64_VERTEX.
This change allows the DDX to map the DMA buffers read-only and eliminate a
security problem where a client can alter the contents of the DMA buffer after
submission to the DRM.
This change also affects the DRI/DRM interface. Performace-wise, it basically
affects PCI mode where I get a ~12% speedup for some Mesa demos I tested.
This is mainly due to eliminating an ioctl for allocating the DMA buffer.
mach64_dma.c: move the responsibility for allocating memory for the DMA ring
in PCI mode to the DDX.
This change affects the DDX/DRM interface and unifies a couple of PCI/AGP code
paths for ring memory in the DRM.
Bump the mach64 DRM version major and date.
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Add DRM_PCI_BUFFER_RO flag for mapping PCI DMA buffer read-only. An additional
flag is needed, since PCI DMA buffers do not have an associated map.
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Factor out from mach64_dma_dispatch_vertex() the code to reclaim an unsed
buffer, in preperation for using it in mach64_dma_dispatch_blit() also.
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Factor out from mach64_freelist_get() the code to reclaim a completed buffer,
this is to improve readability for me.
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Map the DMA buffers from the same linear address as the vertex bufs. If
dev->agp_buffer_token is not set, mach64 drm maps the DMA buffers from
linear address 0x0.
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Initialize the spinlock unconditionally when struct drm_device is filled in,
and return early in drm_locked_tasklet() if the driver doesn't support IRQs.
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This fixes issues on X server startup with versions of xf86-video-intel that
enable the IRQ before they have a context ID.
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It looks like 'after a while', I915REG_INT_IDENTITY_R for some reason always has
VSYNC_PIPEB_FLAG set in the interrupt handler, even though pipe B is disabled.
So we only increase dev->vbl_received if the corresponding bit is also set in
dev->vblank_pipe.
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It looks like this would have caused signals to always get sent on the next
vertical blank, regardless of the sequence number.
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When this flag is set and the target sequence is missed, wait for the next
vertical blank instead of returning immediately.
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Initialize it to default value if it hasn't been set by the X server yet.
In i915_vblank_pipe_set(), only update dev_priv->vblank_pipe and call
i915_enable_interrupt() if the argument passed from userspace is valid to avoid
corrupting dev_priv->vblank_pipe on invalid arguments.
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Handle relative as well as absolute target sequence numbers.
Return error if target sequence has already passed, so userspace can deal with
this situation as it sees fit.
On success, return the sequence number of the vertical blank when the buffer
swap is expected to take place.
Also add DRM_IOCTL_I915_VBLANK_SWAP definition for userspace code that may want
to use ioctl() instead of drmCommandWriteRead().
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This makes it easier for userspace to know when it needs to allocate an ID.
Also free drawable information memory when it's no longer needed.
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This uses the core facility to schedule a driver callback that will be called
ASAP after the given vertical blank interrupt with the HW lock held.
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Also improve diagnostic output.
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Actually make the existing ioctls for adding and removing drawables do
something useful, and add another ioctl for the X server to update drawable
information. The only kind of drawable information tracked so far is cliprects.
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When the vertical blank interrupt is enabled for both pipes, pipe A is
considered primary and pipe B secondary. When it's only enabled for one pipe,
it's always considered primary for backwards compatibility.
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when enabling/disabling vertex programs
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This takes up two more ring buffer entries per rectangle blitted but makes sure
the blit is performed top to bottom, reducing the likelyhood of tearing.
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