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2007-09-21nouveau: add some checks to the nv04 graph switching code.Stephane Marchesin
2007-09-20drm_sysfs: update sysfs code from kernelDave Airlie
2007-09-18i915: Reinstate check that drawable has valid information in i915_vblank_swap.Michel Dänzer
2007-09-18i915: Fix scheduled buffer swaps.Michel Dänzer
One instance of unlocking a spinlock was converted incorrectly when this code was fixed to build on BSD.
2007-09-18Add ioc32 compat layer for XGI DRM.Ian Romanick
2007-09-18Fix ioc32 compat layerIan Romanick
Previously any ioctls that weren't explicitly listed in the compat ioctl table would fail with ENOTTY. If the incoming ioctl number is outside the range of the table, assume that it Just Works, and pass it off to drm_ioctl. This make the fence related ioctls work on 64-bit PowerPC.
2007-09-12Added bool typedef added in kernel 2.6.19Brian
This allows the xgi code to compile with older kernels.
2007-09-12Added idr_replace() function which was apparently added in Linux 2.6.18Brian
Someone should probably double-check my work here since this is the first time I've touched drm_compat.[ch]
2007-09-12Remove plane->pipe mapping from SAREA private after allJesse Barnes
We can figure out which pipe a given plane is mapped to by looking at the display control registers instead of tracking it in a new SAREA private field. If this becomes a performance problem, we could move to an ioctl based solution by adding a new parameter for the DDX to set (defaulting to the old behavior if the param was never set of course).
2007-09-11Merge branch 'master' of ssh://git.freedesktop.org/git/mesa/drmJesse Barnes
2007-09-11Disambiguate planes & pipes for swap operationsJesse Barnes
This mod makes the SAREA track plane to pipe mappings and corrects the name of the plane info variables (they were mislabeled as pipe info since until now all code assumed a direct mapping between planes and pipes). It also updates the flip ioctl argument to take a set of planes rather than pipes, since planes are flipped while pipes generate vblank events.
2007-09-10nouveau: nv10: add combiner registersPatrice Mandin
2007-09-09nouveau : nv10 fix NV10_PGRAPH_CTX_USER save/loadMatthieu Castet
2007-09-09nouveau : nv10 pipe ctx switch load/save.Matthieu Castet
This fix some issues with more than one 3D fifo, but there still some "corruption" sometimes
2007-09-08nouveau: Add Quadro NVS 140 pciidMaarten Maathuis
2007-09-07nouveau: Use nv41 ctxprog/vals on nv42.Ben Skeggs
2007-09-06Merge branch 'xgi-0-0-2'Ian Romanick
2007-09-06Bump version to 1.0.0.Ian Romanick
2007-09-06nouveau: fix some nv04 graph switching.Stephane Marchesin
2007-09-06nouveau: add pure nv30 support.Stephane Marchesin
2007-09-04Add context init voodoo and context switch code for NV41.Maarten Maathuis
2007-08-31Merge branch 'master' of ssh+git://git.freedesktop.org/git/mesa/drm into ↵Ian Romanick
xgi-0-0-2
2007-08-31Acutally emit the IRQ (duh) when setting the fence post.Ian Romanick
2007-08-31nouveau: nv04 context switching support. Works for starting X up at least.Stephane Marchesin
2007-08-31nouveau: give nv03 the last cut.Stephane Marchesin
2007-08-29Use ati_pcigart for PCI-e GART table handling.Ian Romanick
2007-08-29Fix late night dumb-dumb mistake.Ian Romanick
2007-08-29Use DRM_SPINLOCK / DRM_UNSPINLOCK macros.Ian Romanick
2007-08-28Add register defines for hw binningKeith Packard
2007-08-28drm: remove XFREE86_VERSION macrosDave Airlie
2007-08-26nouveau : add NV04_PGRAPH_TRAPPED_ADDR definitionMatthieu Castet
- fix offset for nv04 - use it in nv10 graph ctx switch for getting next channel - dump NV10_PGRAPH_TRAPPED_DATA_HIGH on nv10+
2007-08-25nouveau : nv1x graph reworksMatthieu Castet
- add forgotten init value - use the same PGRAPH_DEBUG than the blob - remove init of ddx reg : it should be done with object - better handle of channel destruction hope I didn't break anything ;)
2007-08-25nouveau: nv10: output a warning if last channel invalid, and switch to nextPatrice Mandin
2007-08-23nouveau: nv10: check some NULL pointers inside context switchPatrice Mandin
2007-08-22nouveau : fix some potential crashes with objects causing hash collisionMatthieu Castet
2007-08-22nouveau/nv40: Preserve other bits in 0x400304/0x400310 like NVIDIA do.Ben Skeggs
2007-08-22nouveau/nv40: Dump extra info on ucode state if ctx switch fails.Ben Skeggs
2007-08-22nouveau: NV4c ctx ucode.Ben Skeggs
Seems we already have a nv4c_ctx_init() somehow, a quick check shows the ucode matches it still.
2007-08-22nouveau/nv50: Correct thinko for 8800 chips + cleanup a bit.Ben Skeggs
2007-08-22nouveau: redo nv30_graph.c. Should work better, but we still lack a couple ↵Stephane Marchesin
of cards.
2007-08-22nouveau: fix the comment and debug message for PCIGART sizeStephane Marchesin
2007-08-21nouveau: Add NV44 ctx ucode. Patch from stillunknown.Ben Skeggs
Microcode is similar enough to the NV4A one that it should be able to use the same initial PGRAPH context. One day this mess will go away, honest..
2007-08-21nouveau: Poke 0x2230 on NV47 also.Ben Skeggs
Makes 0x2220 work the same way as on NV40.
2007-08-19Check also for Linux, as it's not supported on different OSPatrice Mandin
2007-08-19Function pci_get_bus_and_slot needs 2.6.19 or laterPatrice Mandin
2007-08-17Remove unnecessary include.Ian Romanick
2007-08-16Forgot to add this file on the last commit.Ian Romanick
2007-08-17nouveau: Detect memory on NFORCE/NFORCE2 correctly.Ben Skeggs
2007-08-15Implement fence support.Ian Romanick
2007-08-15Fix dev->agp->base initialization on BSD, and fix addmap range check on Linux.Eric Anholt
With the previous linux commit, an AGP aperture at the end of the address space would have wrapped to 0 and the test would have failed.
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 19:17:46 +0000