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-rw-r--r--shared-core/nv20_graph.c140
1 files changed, 138 insertions, 2 deletions
diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c
index 8291f214..213d60cc 100644
--- a/shared-core/nv20_graph.c
+++ b/shared-core/nv20_graph.c
@@ -19,14 +19,146 @@
*
*/
-/*#define NV20_GRCTX_SIZE (3529*4)*/
-
+#define NV20_GRCTX_SIZE (3580*4)
#define NV25_GRCTX_SIZE (3529*4)
#define NV30_31_GRCTX_SIZE (22392)
#define NV34_GRCTX_SIZE (18140)
#define NV35_36_GRCTX_SIZE (22396)
+static void nv20_graph_context_init(struct drm_device *dev,
+ struct nouveau_gpuobj *ctx)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ int i;
+/*
+write32 #1 block at +0x00740adc NV_PRAMIN+0x40adc of 3369 (0xd29) elements:
++0x00740adc: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
++0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
++0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
++0x00740b3c: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000
++0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
++0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
++0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
++0x00740bbc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
++0x00740bdc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
++0x00740bfc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+
++0x00740c1c: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000
++0x00740c3c: 00000000 00000000 00000000 44400000 00000000 00000000 00000000 00000000
++0x00740c5c: 00000000 00000000 00000000 00000000 00000000 00000000 00030303 00030303
++0x00740c7c: 00030303 00030303 00000000 00000000 00000000 00000000 00080000 00080000
++0x00740c9c: 00080000 00080000 00000000 00000000 01012000 01012000 01012000 01012000
++0x00740cbc: 000105b8 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008
++0x00740cdc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
++0x00740cfc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
++0x00740d1c: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
++0x00740d3c: 00000000 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000
+
++0x00740d5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
++0x00740d7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
++0x00740d9c: 00000001 00000000 00004000 00000000 00000000 00000001 00000000 00040000
++0x00740dbc: 00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
++0x00740ddc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+...
+*/
+ INSTANCE_WR(ctx, (0x33c/4)+0, 0xffff0000);
+ INSTANCE_WR(ctx, (0x33c/4)+25, 0x0fff0000);
+ INSTANCE_WR(ctx, (0x33c/4)+26, 0x0fff0000);
+ INSTANCE_WR(ctx, (0x33c/4)+80, 0x00000101);
+ INSTANCE_WR(ctx, (0x33c/4)+85, 0x00000111);
+ INSTANCE_WR(ctx, (0x33c/4)+91, 0x44400000);
+ for (i = 0; i < 4; ++i)
+ INSTANCE_WR(ctx, (0x33c/4)+102+i, 0x00030303);
+ for (i = 0; i < 4; ++i)
+ INSTANCE_WR(ctx, (0x33c/4)+110+i, 0x00080000);
+ for (i = 0; i < 4; ++i)
+ INSTANCE_WR(ctx, (0x33c/4)+116+i, 0x01012000);
+ for (i = 0; i < 4; ++i)
+ INSTANCE_WR(ctx, (0x33c/4)+120+i, 0x000105b8);
+ for (i = 0; i < 4; ++i)
+ INSTANCE_WR(ctx, (0x33c/4)+124+i, 0x00080008);
+ for (i = 0; i < 16; ++i)
+ INSTANCE_WR(ctx, (0x33c/4)+136+i, 0x07ff0000);
+ INSTANCE_WR(ctx, (0x33c/4)+154, 0x4b7ffff);
+ INSTANCE_WR(ctx, (0x33c/4)+176, 0x00000001);
+ INSTANCE_WR(ctx, (0x33c/4)+178, 0x00004000);
+ INSTANCE_WR(ctx, (0x33c/4)+181, 0x00000001);
+ INSTANCE_WR(ctx, (0x33c/4)+183, 0x00004000);
+ INSTANCE_WR(ctx, (0x33c/4)+184, 0x00010000);
+
+/*
+...
++0x0074239c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
++0x007423bc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
++0x007423dc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
++0x007423fc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+...
++0x00742bdc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
++0x00742bfc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
++0x00742c1c: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
++0x00742c3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+...
+*/
+ for (i = 0; i < 0x880; i += 0x10) {
+ INSTANCE_WR(ctx, ((0x1c1c + i)/4)+0, 0x10700ff9);
+ INSTANCE_WR(ctx, ((0x1c1c + i)/4)+1, 0x0436086c);
+ INSTANCE_WR(ctx, ((0x1c1c + i)/4)+2, 0x000c001b);
+ }
+
+/*
+write32 #1 block at +0x00742fbc NV_PRAMIN+0x42fbc of 4 (0x4) elements:
++0x00742fbc: 3f800000 00000000 00000000 00000000
+*/
+ INSTANCE_WR(ctx, (0x281c/4), 0x3f800000);
+
+/*
+write32 #1 block at +0x00742ffc NV_PRAMIN+0x42ffc of 12 (0xc) elements:
++0x00742ffc: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000
++0x0074301c: 00000000 bf800000 00000000 00000000
+*/
+ INSTANCE_WR(ctx, (0x285c/4)+0, 0x40000000);
+ INSTANCE_WR(ctx, (0x285c/4)+1, 0x3f800000);
+ INSTANCE_WR(ctx, (0x285c/4)+2, 0x3f000000);
+ INSTANCE_WR(ctx, (0x285c/4)+4, 0x40000000);
+ INSTANCE_WR(ctx, (0x285c/4)+5, 0x3f800000);
+ INSTANCE_WR(ctx, (0x285c/4)+7, 0xbf800000);
+ INSTANCE_WR(ctx, (0x285c/4)+9, 0xbf800000);
+
+/*
+write32 #1 block at +0x00742fcc NV_PRAMIN+0x42fcc of 4 (0x4) elements:
++0x00742fcc: 00000000 3f800000 00000000 00000000
+*/
+ INSTANCE_WR(ctx, (0x282c/4)+1, 0x3f800000);
+
+/*
+write32 #1 block at +0x0074302c NV_PRAMIN+0x4302c of 4 (0x4) elements:
++0x0074302c: 00000000 00000000 00000000 00000000
+write32 #1 block at +0x00743c9c NV_PRAMIN+0x43c9c of 4 (0x4) elements:
++0x00743c9c: 00000000 00000000 00000000 00000000
+write32 #1 block at +0x00743c3c NV_PRAMIN+0x43c3c of 8 (0x8) elements:
++0x00743c3c: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000
+*/
+ INSTANCE_WR(ctx, (0x349c/4)+2, 0x000fe000);
+
+/*
+write32 #1 block at +0x00743c6c NV_PRAMIN+0x43c6c of 4 (0x4) elements:
++0x00743c6c: 00000000 00000000 00000000 00000000
+write32 #1 block at +0x00743ccc NV_PRAMIN+0x43ccc of 4 (0x4) elements:
++0x00743ccc: 00000000 000003f8 00000000 00000000
+*/
+ INSTANCE_WR(ctx, (0x352c/4)+1, 0x000003f8);
+
+/* write32 #1 NV_PRAMIN+0x43ce0 <- 0x002fe000 */
+ INSTANCE_WR(ctx, 0x3540/4, 0x002fe000);
+
+/*
+write32 #1 block at +0x00743cfc NV_PRAMIN+0x43cfc of 8 (0x8) elements:
++0x00743cfc: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c
+*/
+ for (i = 0; i < 8; ++i)
+ INSTANCE_WR(ctx, (0x355c/4)+i, 0x001c527c);
+}
static void nv25_graph_context_init(struct drm_device *dev,
struct nouveau_gpuobj *ctx)
@@ -2876,6 +3008,10 @@ int nv20_graph_create_context(struct nouveau_channel *chan)
int ret;
switch (dev_priv->chipset) {
+ case 0x20:
+ ctx_size = NV20_GRCTX_SIZE;
+ ctx_init = nv20_graph_context_init;
+ break;
case 0x25:
case 0x28:
ctx_size = NV25_GRCTX_SIZE;