5 files changed, 24 insertions, 23 deletions

diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h
index 522a8cf9..41ea9a54 100644
--- a/shared-core/nouveau_drv.h
+++ b/shared-core/nouveau_drv.h
@@ -104,6 +104,8 @@ struct nouveau_config {
 typedef struct drm_nouveau_private {
 	/* the card type, takes NV_* as values */
 	int card_type;
+	/* exact chipset, derived from NV_PMC_BOOT_0 */
+	int chipset;
 	int flags;
 
 	drm_local_map_t *mmio;
diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c
index fb35ba74..d20dca22 100644
--- a/shared-core/nouveau_state.c
+++ b/shared-core/nouveau_state.c
@@ -83,6 +83,12 @@ int nouveau_firstopen(struct drm_device *dev)
 	} else
 		dev_priv->ramin = NULL;
 
+	/* Determine exact chipset we're running on */
+	if (dev_priv->card_type < NV_10)
+		dev_priv->chipset = dev_priv->card_type;
+	else
+		dev_priv->chipset =(NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20;
+
 	/* Clear RAMIN
 	 * Determine locations for RAMHT/FC/RO
 	 * Initialise PFIFO
diff --git a/shared-core/nv10_graph.c b/shared-core/nv10_graph.c
index c9ff96ea..39aaba60 100644
--- a/shared-core/nv10_graph.c
+++ b/shared-core/nv10_graph.c
@@ -532,7 +532,7 @@ static int nv17_graph_ctx_regs [] = {
 void nouveau_nv10_context_switch(drm_device_t *dev)
 {
 	drm_nouveau_private_t *dev_priv = dev->dev_private;
-	int channel, channel_old, i, j, gpu_type;
+	int channel, channel_old, i, j;
 
 	channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1);
 	channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
@@ -549,10 +549,9 @@ void nouveau_nv10_context_switch(drm_device_t *dev)
 	// save PGRAPH context
 	for (i = 0; nv10_graph_ctx_regs[i]; i++)
 		dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]);
-	gpu_type = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000);
-	if ((gpu_type==0x01700000)
-		|| (gpu_type==0x01800000)
-		|| (gpu_type==0x01f00000))
+	if ((dev_priv->chipset==0x17)
+		|| (dev_priv->chipset==0x18)
+		|| (dev_priv->chipset==0x1f))
 	{
 		for (j = 0; nv17_graph_ctx_regs[j]; i++,j++)
 			dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]);
@@ -569,9 +568,9 @@ void nouveau_nv10_context_switch(drm_device_t *dev)
 #if 1
 	for (i = 0; nv10_graph_ctx_regs[i]; i++)
 		NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]);
-	if ((gpu_type==0x01700000)
-		|| (gpu_type==0x01800000)
-		|| (gpu_type==0x01f00000))
+	if ((dev_priv->chipset==0x17)
+		|| (dev_priv->chipset==0x18)
+		|| (dev_priv->chipset==0x1f))
 	{
 		for (j = 0; nv17_graph_ctx_regs[j]; i++,j++)
 			NV_WRITE(nv17_graph_ctx_regs[j], dev_priv->fifos[channel].nv10_pgraph_ctx[i]);
diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c
index a5f01ea5..143fe965 100644
--- a/shared-core/nv30_graph.c
+++ b/shared-core/nv30_graph.c
@@ -107,10 +107,9 @@ int nv30_graph_context_create(drm_device_t *dev, int channel)
 	struct nouveau_fifo *chan = &dev_priv->fifos[channel];
 	void (*ctx_init)(drm_device_t *, struct mem_block *);
 	unsigned int ctx_size;
-	int i, chipset;
+	int i;
 
-	chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20;
-	switch (chipset) {
+	switch (dev_priv->chipset) {
 	default:
 		ctx_size = NV30_GRCTX_SIZE;
 		ctx_init = nv30_graph_context_init;
@@ -137,10 +136,7 @@ int nv30_graph_init(drm_device_t *dev)
 {
 	drm_nouveau_private_t *dev_priv =
 		(drm_nouveau_private_t *)dev->dev_private;
-	int i, chipset;
-
-	chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20;
-	DRM_DEBUG("chipset (from PMC_BOOT_0): NV%02X\n", chipset);
+	int i;
 
         /* Create Context Pointer Table */
         dev_priv->ctx_table_size = 32 * 4;
diff --git a/shared-core/nv40_graph.c b/shared-core/nv40_graph.c
index 00583cdc..71434e5b 100644
--- a/shared-core/nv40_graph.c
+++ b/shared-core/nv40_graph.c
@@ -611,10 +611,9 @@ nv40_graph_context_create(drm_device_t *dev, int channel)
 	struct nouveau_fifo *chan = &dev_priv->fifos[channel];
 	void (*ctx_init)(drm_device_t *, struct mem_block *);
 	unsigned int ctx_size;
-	int i, chipset;
+	int i;
 
-	chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20;
-	switch (chipset) {
+	switch (dev_priv->chipset) {
 	case 0x40:
 		ctx_size = NV40_GRCTX_SIZE;
 		ctx_init = nv40_graph_context_init;
@@ -896,17 +895,16 @@ nv40_graph_init(drm_device_t *dev)
 		(drm_nouveau_private_t *)dev->dev_private;
 	uint32_t *ctx_voodoo;
 	uint32_t pg0220_inst;
-	int i, chipset;
+	int i;
 
-	chipset = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000) >> 20;
-	DRM_DEBUG("chipset (from PMC_BOOT_0): NV%02X\n", chipset);
-	switch (chipset) {
+	switch (dev_priv->chipset) {
 	case 0x40: ctx_voodoo = nv40_ctx_voodoo; break;
 	case 0x43: ctx_voodoo = nv43_ctx_voodoo; break;
 	case 0x4a: ctx_voodoo = nv4a_ctx_voodoo; break;
 	case 0x4e: ctx_voodoo = nv4e_ctx_voodoo; break;
 	default:
-		DRM_ERROR("Unknown ctx_voodoo for chipset 0x%02x\n", chipset);
+		DRM_ERROR("Unknown ctx_voodoo for chipset 0x%02x\n",
+				dev_priv->chipset);
 		ctx_voodoo = NULL;
 		break;
 	}