diff options
Diffstat (limited to 'shared-core')
| -rw-r--r-- | shared-core/drm.h | 116 | ||||
| -rw-r--r-- | shared-core/i915_dma.c | 4 | ||||
| -rw-r--r-- | shared-core/i915_drv.h | 19 | ||||
| -rw-r--r-- | shared-core/nouveau_fifo.c | 12 | ||||
| -rw-r--r-- | shared-core/nouveau_mem.c | 9 | ||||
| -rw-r--r-- | shared-core/via_dma.c | 14 | ||||
| -rw-r--r-- | shared-core/via_drm.h | 14 | ||||
| -rw-r--r-- | shared-core/via_drv.c | 51 | ||||
| -rw-r--r-- | shared-core/via_drv.h | 51 | ||||
| -rw-r--r-- | shared-core/via_map.c | 17 |
10 files changed, 223 insertions, 84 deletions
diff --git a/shared-core/drm.h b/shared-core/drm.h index 0e3b9b89..447065c7 100644 --- a/shared-core/drm.h +++ b/shared-core/drm.h @@ -678,7 +678,7 @@ typedef struct drm_set_version { typedef struct drm_fence_arg { unsigned handle; - int class; + int class; unsigned type; unsigned flags; unsigned signaled; @@ -697,9 +697,10 @@ typedef struct drm_fence_arg { } drm_fence_arg_t; /* Buffer permissions, referring to how the GPU uses the buffers. - these translate to fence types used for the buffers. - Typically a texture buffer is read, A destination buffer is write and - a command (batch-) buffer is exe. Can be or-ed together. */ + * these translate to fence types used for the buffers. + * Typically a texture buffer is read, A destination buffer is write and + * a command (batch-) buffer is exe. Can be or-ed together. + */ #define DRM_BO_FLAG_READ 0x00000001 #define DRM_BO_FLAG_WRITE 0x00000002 @@ -707,47 +708,82 @@ typedef struct drm_fence_arg { /* * Status flags. Can be read to determine the actual state of a buffer. + * Can also be set in the buffer mask before validation. */ -/* - * Cannot evict this buffer. Not even with force. This type of buffer should - * only be available for root, and must be manually removed before buffer - * manager shutdown or swapout. +/* + * Mask: Never evict this buffer. Not even with force. This type of buffer is only + * available to root and must be manually removed before buffer manager shutdown + * or lock. + * Flags: Acknowledge */ #define DRM_BO_FLAG_NO_EVICT 0x00000010 -/* Always keep a system memory shadow to a vram buffer */ -#define DRM_BO_FLAG_SHADOW_VRAM 0x00000020 -/* The buffer is shareable with other processes */ + +/* + * Mask: Require that the buffer is placed in mappable memory when validated. + * If not set the buffer may or may not be in mappable memory when validated. + * Flags: If set, the buffer is in mappable memory. + */ +#define DRM_BO_FLAG_MAPPABLE 0x00000020 + +/* Mask: The buffer should be shareable with other processes. + * Flags: The buffer is shareable with other processes. + */ #define DRM_BO_FLAG_SHAREABLE 0x00000040 -/* The buffer is currently cached */ + +/* Mask: If set, place the buffer in cache-coherent memory if available. + * If clear, never place the buffer in cache coherent memory if validated. + * Flags: The buffer is currently in cache-coherent memory. + */ #define DRM_BO_FLAG_CACHED 0x00000080 -/* Make sure that every time this buffer is validated, it ends up on the same - * location. The buffer will also not be evicted when claiming space for - * other buffers. Basically a pinned buffer but it may be thrown out as - * part of buffer manager shutdown or swapout. Not supported yet.*/ + +/* Mask: Make sure that every time this buffer is validated, + * it ends up on the same location provided that the memory mask is the same. + * The buffer will also not be evicted when claiming space for + * other buffers. Basically a pinned buffer but it may be thrown out as + * part of buffer manager shutdown or locking. + * Flags: Acknowledge. + */ #define DRM_BO_FLAG_NO_MOVE 0x00000100 -/* Make sure the buffer is in cached memory when mapped for reading */ -#define DRM_BO_FLAG_READ_CACHED 0x00080000 -/* When there is a choice between VRAM and TT, prefer VRAM. - The default behaviour is to prefer TT. */ -#define DRM_BO_FLAG_PREFER_VRAM 0x00040000 -/* Bind this buffer cached if the hardware supports it. */ -#define DRM_BO_FLAG_BIND_CACHED 0x0002000 +/* Mask: Make sure the buffer is in cached memory when mapped for reading. + * Flags: Acknowledge. + */ +#define DRM_BO_FLAG_READ_CACHED 0x00080000 -/* System Memory */ +/* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set. + * Flags: Acknowledge. + */ +#define DRM_BO_FLAG_FORCE_CACHING 0x00002000 + +/* + * Mask: Force DRM_BO_FLAG_MAPPABLE flag strictly also if it is clear. + * Flags: Acknowledge. + */ +#define DRM_BO_FLAG_FORCE_MAPPABLE 0x00004000 + +/* + * Memory type flags that can be or'ed together in the mask, but only + * one appears in flags. + */ + +/* System memory */ #define DRM_BO_FLAG_MEM_LOCAL 0x01000000 /* Translation table memory */ #define DRM_BO_FLAG_MEM_TT 0x02000000 /* Vram memory */ #define DRM_BO_FLAG_MEM_VRAM 0x04000000 -/* Unmappable Vram memory */ -#define DRM_BO_FLAG_MEM_VRAM_NM 0x08000000 +/* Up to the driver to define. */ +#define DRM_BO_FLAG_MEM_PRIV0 0x08000000 +#define DRM_BO_FLAG_MEM_PRIV1 0x10000000 +#define DRM_BO_FLAG_MEM_PRIV2 0x20000000 +#define DRM_BO_FLAG_MEM_PRIV3 0x40000000 +#define DRM_BO_FLAG_MEM_PRIV4 0x80000000 + /* Memory flag mask */ #define DRM_BO_MASK_MEM 0xFF000000 +#define DRM_BO_MASK_MEMTYPE 0xFF0000A0 -/* When creating a buffer, Avoid system storage even if allowed */ -#define DRM_BO_HINT_AVOID_LOCAL 0x00000001 /* Don't block on validate and map */ #define DRM_BO_HINT_DONT_BLOCK 0x00000002 /* Don't place this buffer on the unfenced list.*/ @@ -756,9 +792,6 @@ typedef struct drm_fence_arg { #define DRM_BO_HINT_ALLOW_UNFENCED_MAP 0x00000010 -/* Driver specific flags. Could be for example rendering engine */ -#define DRM_BO_MASK_DRIVER 0x00F00000 - typedef enum { drm_bo_type_dc, drm_bo_type_user, @@ -774,7 +807,7 @@ typedef struct drm_bo_arg_request { drm_bo_type_t type; unsigned arg_handle; drm_u64_t buffer_start; - unsigned page_alignment; + unsigned page_alignment; unsigned expand_pad[4]; /*Future expansion */ enum { drm_bo_create, @@ -805,11 +838,11 @@ typedef struct drm_bo_arg_reply { drm_u64_t size; drm_u64_t offset; drm_u64_t arg_handle; - unsigned mask; - drm_u64_t buffer_start; - unsigned fence_flags; - unsigned rep_flags; - unsigned page_alignment; + unsigned mask; + drm_u64_t buffer_start; + unsigned fence_flags; + unsigned rep_flags; + unsigned page_alignment; unsigned expand_pad[4]; /*Future expansion */ }drm_bo_arg_reply_t; @@ -826,8 +859,13 @@ typedef struct drm_bo_arg{ #define DRM_BO_MEM_LOCAL 0 #define DRM_BO_MEM_TT 1 #define DRM_BO_MEM_VRAM 2 -#define DRM_BO_MEM_VRAM_NM 3 -#define DRM_BO_MEM_TYPES 2 /* For now. */ +#define DRM_BO_MEM_PRIV0 3 +#define DRM_BO_MEM_PRIV1 4 +#define DRM_BO_MEM_PRIV2 5 +#define DRM_BO_MEM_PRIV3 6 +#define DRM_BO_MEM_PRIV4 7 + +#define DRM_BO_MEM_TYPES 8 /* For now. */ typedef union drm_mm_init_arg{ struct { diff --git a/shared-core/i915_dma.c b/shared-core/i915_dma.c index 7e2fbd7d..81f1a117 100644 --- a/shared-core/i915_dma.c +++ b/shared-core/i915_dma.c @@ -444,7 +444,7 @@ static void i915_emit_breadcrumb(drm_device_t *dev) OUT_RING(0); ADVANCE_LP_RING(); #ifdef I915_HAVE_FENCE - drm_fence_flush_old(dev, dev_priv->counter); + drm_fence_flush_old(dev, 0, dev_priv->counter); #endif } @@ -591,7 +591,7 @@ static int i915_dispatch_flip(drm_device_t * dev) OUT_RING(0); ADVANCE_LP_RING(); #ifdef I915_HAVE_FENCE - drm_fence_flush_old(dev, dev_priv->counter); + drm_fence_flush_old(dev, 0, dev_priv->counter); #endif dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; return 0; diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h index 5a76cb15..3cb1a573 100644 --- a/shared-core/i915_drv.h +++ b/shared-core/i915_drv.h @@ -126,7 +126,9 @@ typedef struct drm_i915_private { uint32_t flush_pending; uint32_t saved_flush_status; #endif - +#ifdef I915_HAVE_BUFFER + void *agp_iomap; +#endif spinlock_t swaps_lock; drm_i915_vbl_swap_t vbl_swaps; unsigned int swaps_pending; @@ -183,17 +185,25 @@ extern void i915_mem_release(drm_device_t * dev, extern void i915_fence_handler(drm_device_t *dev); -extern int i915_fence_emit_sequence(drm_device_t *dev, uint32_t flags, +extern int i915_fence_emit_sequence(drm_device_t *dev, uint32_t class, + uint32_t flags, uint32_t *sequence, uint32_t *native_type); -extern void i915_poke_flush(drm_device_t *dev); +extern void i915_poke_flush(drm_device_t *dev, uint32_t class); +extern int i915_fence_has_irq(drm_device_t *dev, uint32_t class, uint32_t flags); #endif #ifdef I915_HAVE_BUFFER /* i915_buffer.c */ extern drm_ttm_backend_t *i915_create_ttm_backend_entry(drm_device_t *dev); -extern int i915_fence_types(uint32_t buffer_flags, uint32_t *class, uint32_t *type); +extern int i915_fence_types(drm_buffer_object_t *bo, uint32_t *class, uint32_t *type); extern int i915_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags); +extern int i915_init_mem_type(drm_device_t *dev, uint32_t type, + drm_mem_type_manager_t *man); +extern uint32_t i915_evict_mask(drm_buffer_object_t *bo); +extern int i915_move(drm_buffer_object_t *bo, int evict, + int no_wait, drm_bo_mem_reg_t *new_mem); + #endif #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) @@ -331,6 +341,7 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller); #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) +#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 7f929c5c..fd5455bf 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -187,7 +187,7 @@ int nouveau_fifo_init(drm_device_t *dev) NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 | #ifdef __BIG_ENDIAN - NV_PFIFO_CACH1_BIG_ENDIAN | + NV_PFIFO_CACHE1_BIG_ENDIAN | #endif 0x00000000); @@ -293,7 +293,7 @@ static void nouveau_nv04_context_init(drm_device_t *dev, NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 | #ifdef __BIG_ENDIAN - NV_PFIFO_CACH1_BIG_ENDIAN | + NV_PFIFO_CACHE1_BIG_ENDIAN | #endif 0x00000000); } @@ -326,7 +326,7 @@ static void nouveau_nv10_context_init(drm_device_t *dev, NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 | #ifdef __BIG_ENDIAN - NV_PFIFO_CACH1_BIG_ENDIAN | + NV_PFIFO_CACHE1_BIG_ENDIAN | #endif 0x00000000); } @@ -357,7 +357,7 @@ static void nouveau_nv30_context_init(drm_device_t *dev, NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | #ifdef __BIG_ENDIAN - NV_PFIFO_CACH1_BIG_ENDIAN | + NV_PFIFO_CACHE1_BIG_ENDIAN | #endif 0x00000000); @@ -421,7 +421,7 @@ static void nouveau_nv40_context_init(drm_device_t *dev, NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 | #ifdef __BIG_ENDIAN - NV_PFIFO_CACH1_BIG_ENDIAN | + NV_PFIFO_CACHE1_BIG_ENDIAN | #endif 0x30000000 /* no idea.. */); RAMFC_WR(DMA_SUBROUTINE, init->put_base); @@ -493,7 +493,7 @@ nouveau_fifo_context_restore(drm_device_t *dev, int channel) NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 | #ifdef __BIG_ENDIAN - NV_PFIFO_CACH1_BIG_ENDIAN | + NV_PFIFO_CACHE1_BIG_ENDIAN | #endif 0x00000000); } diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index cd53d25d..3b1f443c 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -35,7 +35,7 @@ #include "drm_sarea.h" #include "nouveau_drv.h" -static int meminit_ok=0; +//static int meminit_ok=0; static struct mem_block *split_block(struct mem_block *p, uint64_t start, uint64_t size, DRMFILE filp) @@ -373,10 +373,9 @@ struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment, uint6 /* * Init memory if needed */ - if (meminit_ok==0) + if (dev_priv->fb_phys == 0) { nouveau_mem_init(dev); - meminit_ok=1; } /* @@ -446,8 +445,10 @@ alloc_ok: void nouveau_mem_free(struct drm_device* dev, struct mem_block* block) { + drm_nouveau_private_t *dev_priv = dev->dev_private; + DRM_INFO("freeing 0x%llx\n", block->start); - if (meminit_ok==0) + if (dev_priv->fb_phys == 0) { DRM_ERROR("%s called without init\n", __FUNCTION__); return; diff --git a/shared-core/via_dma.c b/shared-core/via_dma.c index 09159634..8c5a5c64 100644 --- a/shared-core/via_dma.c +++ b/shared-core/via_dma.c @@ -40,20 +40,6 @@ #include "via_drv.h" #include "via_3d_reg.h" -#define CMDBUF_ALIGNMENT_SIZE (0x100) -#define CMDBUF_ALIGNMENT_MASK (0x0ff) - -/* defines for VIA 3D registers */ -#define VIA_REG_STATUS 0x400 -#define VIA_REG_TRANSET 0x43C -#define VIA_REG_TRANSPACE 0x440 - -/* VIA_REG_STATUS(0x400): Engine Status */ -#define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */ -#define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */ -#define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */ -#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */ - #define SetReg2DAGP(nReg, nData) { \ *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \ *((uint32_t *)(vb) + 1) = (nData); \ diff --git a/shared-core/via_drm.h b/shared-core/via_drm.h index 88345bdf..635e4637 100644 --- a/shared-core/via_drm.h +++ b/shared-core/via_drm.h @@ -58,21 +58,11 @@ (VIA_MAX_CACHELINE_SIZE - 1)) & \ ~(VIA_MAX_CACHELINE_SIZE - 1)) + \ VIA_MAX_CACHELINE_SIZE*(lockNo))) - -/* Each region is a minimum of 64k, and there are at most 64 of them. - */ #define VIA_NR_TEX_REGIONS 64 -#define VIA_LOG_MIN_TEX_REGION_SIZE 16 + #endif -#define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ -#define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ -#define VIA_UPLOAD_CTX 0x4 -#define VIA_UPLOAD_BUFFERS 0x8 -#define VIA_UPLOAD_TEX0 0x10 -#define VIA_UPLOAD_TEX1 0x20 -#define VIA_UPLOAD_CLIPRECTS 0x40 -#define VIA_UPLOAD_ALL 0xff +#define DRM_VIA_FENCE_TYPE_ACCEL 0x00000002 /* VIA specific ioctls */ #define DRM_VIA_ALLOCMEM 0x00 diff --git a/shared-core/via_drv.c b/shared-core/via_drv.c index 33b0a42d..0a478fef 100644 --- a/shared-core/via_drv.c +++ b/shared-core/via_drv.c @@ -38,6 +38,47 @@ static struct pci_device_id pciidlist[] = { viadrv_PCI_IDS }; + +#ifdef VIA_HAVE_FENCE +static drm_fence_driver_t via_fence_driver = { + .num_classes = 1, + .wrap_diff = (1 << 30), + .flush_diff = (1 << 20), + .sequence_mask = 0xffffffffU, + .lazy_capable = 1, + .emit = via_fence_emit_sequence, + .poke_flush = via_poke_flush, + .has_irq = via_fence_has_irq, +}; +#endif +#ifdef VIA_HAVE_BUFFER + +/** + * If there's no thrashing. This is the preferred memory type order. + */ +static uint32_t via_mem_prios[] = {DRM_BO_MEM_PRIV0, DRM_BO_MEM_VRAM, DRM_BO_MEM_TT, DRM_BO_MEM_LOCAL}; + +/** + * If we have thrashing, most memory will be evicted to TT anyway, so we might as well + * just move the new buffer into TT from the start. + */ +static uint32_t via_busy_prios[] = {DRM_BO_MEM_TT, DRM_BO_MEM_PRIV0, DRM_BO_MEM_VRAM, DRM_BO_MEM_LOCAL}; + + +static drm_bo_driver_t via_bo_driver = { + .mem_type_prio = via_mem_prios, + .mem_busy_prio = via_busy_prios, + .num_mem_type_prio = ARRAY_SIZE(via_mem_prios), + .num_mem_busy_prio = ARRAY_SIZE(via_busy_prios), + .create_ttm_backend_entry = via_create_ttm_backend_entry, + .fence_type = via_fence_types, + .invalidate_caches = via_invalidate_caches, + .init_mem_type = via_init_mem_type, + .evict_mask = via_evict_mask, + .move = NULL, +}; +#endif + static int probe(struct pci_dev *pdev, const struct pci_device_id *ent); static struct drm_driver driver = { .driver_features = @@ -57,8 +98,9 @@ static struct drm_driver driver = { .dma_quiescent = via_driver_dma_quiescent, .dri_library_name = dri_library_name, .reclaim_buffers = drm_core_reclaim_buffers, + .reclaim_buffers_locked = NULL, #ifdef VIA_HAVE_CORE_MM - .reclaim_buffers_locked = via_reclaim_buffers_locked, + .reclaim_buffers_idlelocked = via_reclaim_buffers_locked, .lastclose = via_lastclose, #endif .get_map_ofs = drm_core_get_map_ofs, @@ -79,7 +121,12 @@ static struct drm_driver driver = { .probe = probe, .remove = __devexit_p(drm_cleanup_pci), }, - +#ifdef VIA_HAVE_FENCE + .fence_driver = &via_fence_driver, +#endif +#ifdef VIA_HAVE_BUFFER + .bo_driver = &via_bo_driver, +#endif .name = DRIVER_NAME, .desc = DRIVER_DESC, .date = VIA_DRM_DRIVER_DATE, diff --git a/shared-core/via_drv.h b/shared-core/via_drv.h index 42d0c749..baafbbff 100644 --- a/shared-core/via_drv.h +++ b/shared-core/via_drv.h @@ -32,6 +32,27 @@ #include "via_verifier.h" +/* + * Registers go here. + */ + + +#define CMDBUF_ALIGNMENT_SIZE (0x100) +#define CMDBUF_ALIGNMENT_MASK (0x0ff) + +/* defines for VIA 3D registers */ +#define VIA_REG_STATUS 0x400 +#define VIA_REG_TRANSET 0x43C +#define VIA_REG_TRANSPACE 0x440 + +/* VIA_REG_STATUS(0x400): Engine Status */ +#define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */ +#define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */ +#define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */ +#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */ + + + #if defined(__linux__) #include "via_dmablit.h" @@ -41,6 +62,8 @@ */ #define VIA_HAVE_DMABLIT 1 #define VIA_HAVE_CORE_MM 1 +#define VIA_HAVE_FENCE 1 +#define VIA_HAVE_BUFFER 1 #endif #define VIA_PCI_BUF_SIZE 60000 @@ -103,6 +126,12 @@ typedef struct drm_via_private { drm_via_blitq_t blit_queues[VIA_NUM_BLIT_ENGINES]; #endif uint32_t dma_diff; +#ifdef VIA_HAVE_FENCE + spinlock_t fence_lock; + uint32_t emit_0_sequence; + int have_idlelock; + struct timer_list fence_timer; +#endif } drm_via_private_t; enum via_family { @@ -163,4 +192,26 @@ extern void via_dmablit_handler(drm_device_t *dev, int engine, int from_irq); extern void via_init_dmablit(drm_device_t *dev); #endif +#ifdef VIA_HAVE_FENCE +extern void via_fence_timer(unsigned long data); +extern void via_poke_flush(drm_device_t * dev, uint32_t class); +extern int via_fence_emit_sequence(drm_device_t * dev, uint32_t class, + uint32_t flags, + uint32_t * sequence, + uint32_t * native_type); +extern int via_fence_has_irq(struct drm_device * dev, uint32_t class, + uint32_t flags); +#endif + +#ifdef VIA_HAVE_BUFFER +extern drm_ttm_backend_t *via_create_ttm_backend_entry(drm_device_t *dev); +extern int via_fence_types(drm_buffer_object_t *bo, uint32_t *class, uint32_t *type); +extern int via_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags); +extern int via_init_mem_type(drm_device_t *dev, uint32_t type, + drm_mem_type_manager_t *man); +extern uint32_t via_evict_mask(drm_buffer_object_t *bo); +extern int via_move(drm_buffer_object_t *bo, int evict, + int no_wait, drm_bo_mem_reg_t *new_mem); +#endif + #endif diff --git a/shared-core/via_map.c b/shared-core/via_map.c index a37f5fd2..83324cfa 100644 --- a/shared-core/via_map.c +++ b/shared-core/via_map.c @@ -28,6 +28,7 @@ static int via_do_init_map(drm_device_t * dev, drm_via_init_t * init) { drm_via_private_t *dev_priv = dev->dev_private; + int ret = 0; DRM_DEBUG("%s\n", __FUNCTION__); @@ -64,8 +65,22 @@ static int via_do_init_map(drm_device_t * dev, drm_via_init_t * init) #ifdef VIA_HAVE_DMABLIT via_init_dmablit( dev ); #endif +#ifdef VIA_HAVE_FENCE + dev_priv->emit_0_sequence = 0; + dev_priv->have_idlelock = 0; + spin_lock_init(&dev_priv->fence_lock); + init_timer(&dev_priv->fence_timer); + dev_priv->fence_timer.function = &via_fence_timer; + dev_priv->fence_timer.data = (unsigned long) dev; +#endif /* VIA_HAVE_FENCE */ dev->dev_private = (void *)dev_priv; - return 0; +#ifdef VIA_HAVE_BUFFER + ret = drm_bo_driver_init(dev); + if (ret) + DRM_ERROR("Could not initialize buffer object driver.\n"); +#endif + return ret; + } int via_do_cleanup_map(drm_device_t * dev) |