diff options
Diffstat (limited to 'shared-core/radeon_drv.h')
| -rw-r--r-- | shared-core/radeon_drv.h | 90 |
1 files changed, 45 insertions, 45 deletions
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index efe702a7..c5a84439 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -123,7 +123,7 @@ enum radeon_family { CHIP_RV380, CHIP_R420, CHIP_RV410, - CHIP_RS400, + CHIP_RS480, CHIP_RS690, CHIP_RV515, CHIP_R520, @@ -463,9 +463,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, #define RADEON_PCIE_TX_GART_END_LO 0x16 #define RADEON_PCIE_TX_GART_END_HI 0x17 -#define RS400_NB_MC_INDEX 0x168 -# define RS400_NB_MC_IND_WR_EN (1 << 8) -#define RS400_NB_MC_DATA 0x16c +#define RS480_NB_MC_INDEX 0x168 +# define RS480_NB_MC_IND_WR_EN (1 << 8) +#define RS480_NB_MC_DATA 0x16c #define RS690_MC_INDEX 0x78 # define RS690_MC_INDEX_MASK 0x1ff @@ -474,42 +474,42 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, #define RS690_MC_DATA 0x7c /* MC indirect registers */ -#define RS400_MC_MISC_CNTL 0x18 -# define RS400_DISABLE_GTW (1 << 1) +#define RS480_MC_MISC_CNTL 0x18 +# define RS480_DISABLE_GTW (1 << 1) /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ -# define RS400_GART_INDEX_REG_EN (1 << 12) +# define RS480_GART_INDEX_REG_EN (1 << 12) # define RS690_BLOCK_GFX_D3_EN (1 << 14) -#define RS400_K8_FB_LOCATION 0x1e -#define RS400_GART_FEATURE_ID 0x2b -# define RS400_HANG_EN (1 << 11) -# define RS400_TLB_ENABLE (1 << 18) -# define RS400_P2P_ENABLE (1 << 19) -# define RS400_GTW_LAC_EN (1 << 25) -# define RS400_2LEVEL_GART (0 << 30) -# define RS400_1LEVEL_GART (1 << 30) -# define RS400_PDC_EN (1 << 31) -#define RS400_GART_BASE 0x2c -#define RS400_GART_CACHE_CNTRL 0x2e -# define RS400_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ -#define RS400_AGP_ADDRESS_SPACE_SIZE 0x38 -# define RS400_GART_EN (1 << 0) -# define RS400_VA_SIZE_32MB (0 << 1) -# define RS400_VA_SIZE_64MB (1 << 1) -# define RS400_VA_SIZE_128MB (2 << 1) -# define RS400_VA_SIZE_256MB (3 << 1) -# define RS400_VA_SIZE_512MB (4 << 1) -# define RS400_VA_SIZE_1GB (5 << 1) -# define RS400_VA_SIZE_2GB (6 << 1) -#define RS400_AGP_MODE_CNTL 0x39 -# define RS400_POST_GART_Q_SIZE (1 << 18) -# define RS400_NONGART_SNOOP (1 << 19) -# define RS400_AGP_RD_BUF_SIZE (1 << 20) -# define RS400_REQ_TYPE_SNOOP_SHIFT 22 -# define RS400_REQ_TYPE_SNOOP_MASK 0x3 -# define RS400_REQ_TYPE_SNOOP_DIS (1 << 24) -#define RS400_MC_MISC_UMA_CNTL 0x5f -#define RS400_MC_MCLK_CNTL 0x7a -#define RS400_MC_UMA_DUALCH_CNTL 0x86 +#define RS480_K8_FB_LOCATION 0x1e +#define RS480_GART_FEATURE_ID 0x2b +# define RS480_HANG_EN (1 << 11) +# define RS480_TLB_ENABLE (1 << 18) +# define RS480_P2P_ENABLE (1 << 19) +# define RS480_GTW_LAC_EN (1 << 25) +# define RS480_2LEVEL_GART (0 << 30) +# define RS480_1LEVEL_GART (1 << 30) +# define RS480_PDC_EN (1 << 31) +#define RS480_GART_BASE 0x2c +#define RS480_GART_CACHE_CNTRL 0x2e +# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ +#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 +# define RS480_GART_EN (1 << 0) +# define RS480_VA_SIZE_32MB (0 << 1) +# define RS480_VA_SIZE_64MB (1 << 1) +# define RS480_VA_SIZE_128MB (2 << 1) +# define RS480_VA_SIZE_256MB (3 << 1) +# define RS480_VA_SIZE_512MB (4 << 1) +# define RS480_VA_SIZE_1GB (5 << 1) +# define RS480_VA_SIZE_2GB (6 << 1) +#define RS480_AGP_MODE_CNTL 0x39 +# define RS480_POST_GART_Q_SIZE (1 << 18) +# define RS480_NONGART_SNOOP (1 << 19) +# define RS480_AGP_RD_BUF_SIZE (1 << 20) +# define RS480_REQ_TYPE_SNOOP_SHIFT 22 +# define RS480_REQ_TYPE_SNOOP_MASK 0x3 +# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) +#define RS480_MC_MISC_UMA_CNTL 0x5f +#define RS480_MC_MCLK_CNTL 0x7a +#define RS480_MC_UMA_DUALCH_CNTL 0x86 #define RS690_MC_FB_LOCATION 0x100 #define RS690_MC_AGP_LOCATION 0x101 @@ -530,7 +530,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, #define RADEON_MEM_CNTL 0x0140 #define RADEON_MEM_SDRAM_MODE_REG 0x0158 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */ -#define RS400_AGP_BASE_2 0x0164 +#define RS480_AGP_BASE_2 0x0164 #define RADEON_AGP_BASE 0x0170 /* pipe config regs */ @@ -1183,12 +1183,12 @@ do { \ RADEON_WRITE(R520_MC_IND_INDEX, 0); \ } while (0) -#define RS400_WRITE_MCIND( addr, val ) \ +#define RS480_WRITE_MCIND( addr, val ) \ do { \ - RADEON_WRITE( RS400_NB_MC_INDEX, \ - ((addr) & 0xff) | RS400_NB_MC_IND_WR_EN); \ - RADEON_WRITE( RS400_NB_MC_DATA, (val) ); \ - RADEON_WRITE( RS400_NB_MC_INDEX, 0xff ); \ + RADEON_WRITE( RS480_NB_MC_INDEX, \ + ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ + RADEON_WRITE( RS480_NB_MC_DATA, (val) ); \ + RADEON_WRITE( RS480_NB_MC_INDEX, 0xff ); \ } while (0) #define RS690_WRITE_MCIND( addr, val ) \ @@ -1203,7 +1203,7 @@ do { \ if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \ RS690_WRITE_MCIND( addr, val ); \ else \ - RS400_WRITE_MCIND( addr, val ); \ + RS480_WRITE_MCIND( addr, val ); \ } while (0) #define CP_PACKET0( reg, n ) \ |