diff options
Diffstat (limited to 'shared-core/radeon_cp.c')
| -rw-r--r-- | shared-core/radeon_cp.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 33c928b1..bd54ef6e 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -16310,28 +16310,27 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) static void radeon_init_pipes(drm_radeon_private_t * dev_priv) { - int num_gb_pipes; uint32_t gb_tile_config, gb_pipe_sel = 0; /* RS4xx/RS6xx/R4xx/R5xx */ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); - num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; + dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; } else { /* R3xx */ if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) { - num_gb_pipes = 2; + dev_priv->num_gb_pipes = 2; } else { /* R3Vxx */ - num_gb_pipes = 1; + dev_priv->num_gb_pipes = 1; } } - DRM_INFO("Num pipes: %d\n", num_gb_pipes); + DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes); gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/); - switch(num_gb_pipes) { + switch(dev_priv->num_gb_pipes) { case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; @@ -16341,7 +16340,7 @@ static void radeon_init_pipes(drm_radeon_private_t * dev_priv) if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); - RADEON_WRITE(R500_SU_REG_DEST, ((1 << num_gb_pipes) - 1)); + RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); } RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config); radeon_do_wait_for_idle(dev_priv); |