1 files changed, 19 insertions, 17 deletions

diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c
index 6f25349c..eed3e45b 100644
--- a/shared-core/nv40_fifo.c
+++ b/shared-core/nv40_fifo.c
@@ -28,8 +28,11 @@
 #include "nouveau_drv.h"
 #include "nouveau_drm.h"
 
-#define RAMFC_WR(offset, val)	NV_WI32(fifoctx + NV40_RAMFC_##offset, (val))
-#define RAMFC_RD(offset)	NV_RI32(fifoctx + NV40_RAMFC_##offset)
+
+#define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \
+					 NV40_RAMFC_##offset/4, (val))
+#define RAMFC_RD(offset)     INSTANCE_RD(chan->ramfc->gpuobj, \
+					 NV40_RAMFC_##offset/4)
 #define NV40_RAMFC(c) (dev_priv->ramfc_offset + ((c)*NV40_RAMFC__SIZE))
 #define NV40_RAMFC__SIZE 128
 
@@ -38,21 +41,21 @@ nv40_fifo_create_context(drm_device_t *dev, int channel)
 {
 	drm_nouveau_private_t *dev_priv = dev->dev_private;
 	struct nouveau_fifo *chan = &dev_priv->fifos[channel];
-	uint32_t fifoctx = NV40_RAMFC(channel), grctx, pushbuf;
-	int i;
-
-	for (i = 0; i < NV40_RAMFC__SIZE; i+=4)
-		NV_WI32(fifoctx + i, 0);
+	int ret;
 
-	grctx   = nouveau_chip_instance_get(dev, chan->ramin_grctx);
-	pushbuf = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance);
+	if ((ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(channel),
+						NV40_RAMFC__SIZE,
+						NVOBJ_FLAG_ZERO_ALLOC |
+						NVOBJ_FLAG_ZERO_FREE,
+						NULL, &chan->ramfc)))
+		return ret;
 
 	/* Fill entries that are seen filled in dumps of nvidia driver just
 	 * after channel's is put into DMA mode
 	 */
 	RAMFC_WR(DMA_PUT       , chan->pushbuf_base);
 	RAMFC_WR(DMA_GET       , chan->pushbuf_base);
-	RAMFC_WR(DMA_INSTANCE  , pushbuf);
+	RAMFC_WR(DMA_INSTANCE  , chan->pushbuf->instance >> 4);
 	RAMFC_WR(DMA_FETCH     , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 				 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 				 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
@@ -61,7 +64,7 @@ nv40_fifo_create_context(drm_device_t *dev, int channel)
 #endif
 				 0x30000000 /* no idea.. */);
 	RAMFC_WR(DMA_SUBROUTINE, 0);
-	RAMFC_WR(GRCTX_INSTANCE, grctx);
+	RAMFC_WR(GRCTX_INSTANCE, chan->ramin_grctx->instance >> 4);
 	RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF);
 
 	return 0;
@@ -71,18 +74,17 @@ void
 nv40_fifo_destroy_context(drm_device_t *dev, int channel)
 {
 	drm_nouveau_private_t *dev_priv = dev->dev_private;
-	uint32_t fifoctx = NV40_RAMFC(channel);
-	int i;
+	struct nouveau_fifo *chan = &dev_priv->fifos[channel];
 
-	for (i = 0; i < NV40_RAMFC__SIZE; i+=4)
-		NV_WI32(fifoctx + i, 0);
+	if (chan->ramfc)
+		nouveau_gpuobj_ref_del(dev, &chan->ramfc);
 }
 
 int
 nv40_fifo_load_context(drm_device_t *dev, int channel)
 {
 	drm_nouveau_private_t *dev_priv = dev->dev_private;
-	uint32_t fifoctx = NV40_RAMFC(channel);
+	struct nouveau_fifo *chan = &dev_priv->fifos[channel];
 	uint32_t tmp, tmp2;
 
 	NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET          , RAMFC_RD(DMA_GET));
@@ -141,7 +143,7 @@ int
 nv40_fifo_save_context(drm_device_t *dev, int channel)
 {
 	drm_nouveau_private_t *dev_priv = dev->dev_private;
-	uint32_t fifoctx = NV40_RAMFC(channel);
+	struct nouveau_fifo *chan = &dev_priv->fifos[channel];
 	uint32_t tmp;
 
 	RAMFC_WR(DMA_PUT          , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));