1 files changed, 182 insertions, 193 deletions

diff --git a/shared-core/nouveau_irq.c b/shared-core/nouveau_irq.c
index 8de6e705..e64677ed 100644
--- a/shared-core/nouveau_irq.c
+++ b/shared-core/nouveau_irq.c
@@ -36,132 +36,34 @@
 #include "nouveau_drv.h"
 #include "nouveau_reg.h"
 
-void nouveau_irq_preinstall(drm_device_t *dev)
+void nouveau_irq_preinstall(struct drm_device *dev)
 {
-	drm_nouveau_private_t *dev_priv = dev->dev_private;
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-	DRM_DEBUG("IRQ: preinst\n");
-
-	if (!dev_priv) {
-		DRM_ERROR("AIII, no dev_priv\n");
-		return;
-	}
-	if (!dev_priv->mmio) {
-		DRM_ERROR("AIII, no dev_priv->mmio\n");
-		return;
-	}
-
-	/* Disable/Clear PFIFO interrupts */
-	NV_WRITE(NV03_PFIFO_INTR_EN_0, 0);
-	NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF);
-	/* Disable/Clear PGRAPH interrupts */
-	if (dev_priv->card_type<NV_40)
-		NV_WRITE(NV03_PGRAPH_INTR_EN, 0);
-	else
-		NV_WRITE(NV40_PGRAPH_INTR_EN, 0);
-	NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF);
-#if 0
-	/* Disable/Clear CRTC0/1 interrupts */
-	NV_WRITE(NV_CRTC0_INTEN, 0);
-	NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
-	NV_WRITE(NV_CRTC1_INTEN, 0);
-	NV_WRITE(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
-#endif
 	/* Master disable */
 	NV_WRITE(NV03_PMC_INTR_EN_0, 0);
 }
 
-void nouveau_irq_postinstall(drm_device_t *dev)
+void nouveau_irq_postinstall(struct drm_device *dev)
 {
-	drm_nouveau_private_t *dev_priv = dev->dev_private;
-
-	if (!dev_priv) {
-		DRM_ERROR("AIII, no dev_priv\n");
-		return;
-	}
-	if (!dev_priv->mmio) {
-		DRM_ERROR("AIII, no dev_priv->mmio\n");
-		return;
-	}
-
-	DRM_DEBUG("IRQ: postinst\n");
-
-	/* Enable PFIFO error reporting */
-	NV_WRITE(NV03_PFIFO_INTR_EN_0 , 
-			NV_PFIFO_INTR_CACHE_ERROR |
-			NV_PFIFO_INTR_RUNOUT |
-			NV_PFIFO_INTR_RUNOUT_OVERFLOW |
-			NV_PFIFO_INTR_DMA_PUSHER |
-			NV_PFIFO_INTR_DMA_PT |
-			NV_PFIFO_INTR_SEMAPHORE |
-			NV_PFIFO_INTR_ACQUIRE_TIMEOUT
-			);
-	NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF);
-
-	/* Enable PGRAPH interrupts */
-	if (dev_priv->card_type<NV_40)
-		NV_WRITE(NV03_PGRAPH_INTR_EN,
-				NV_PGRAPH_INTR_NOTIFY |
-				NV_PGRAPH_INTR_MISSING_HW |
-				NV_PGRAPH_INTR_CONTEXT_SWITCH |
-				NV_PGRAPH_INTR_BUFFER_NOTIFY |
-				NV_PGRAPH_INTR_ERROR
-				);
-	else
-		NV_WRITE(NV40_PGRAPH_INTR_EN,
-				NV_PGRAPH_INTR_NOTIFY |
-				NV_PGRAPH_INTR_MISSING_HW |
-				NV_PGRAPH_INTR_CONTEXT_SWITCH |
-				NV_PGRAPH_INTR_BUFFER_NOTIFY |
-				NV_PGRAPH_INTR_ERROR
-				);
-	NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF);
-
-#if 0
-	/* Enable CRTC0/1 interrupts */
-	NV_WRITE(NV_CRTC0_INTEN, NV_CRTC_INTR_VBLANK);
-	NV_WRITE(NV_CRTC1_INTEN, NV_CRTC_INTR_VBLANK);
-#endif
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
 	/* Master enable */
 	NV_WRITE(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
 }
 
-void nouveau_irq_uninstall(drm_device_t *dev)
+void nouveau_irq_uninstall(struct drm_device *dev)
 {
-	drm_nouveau_private_t *dev_priv = dev->dev_private;
-
-	if (!dev_priv) {
-		DRM_ERROR("AIII, no dev_priv\n");
-		return;
-	}
-	if (!dev_priv->mmio) {
-		DRM_ERROR("AIII, no dev_priv->mmio\n");
-		return;
-	}
-
-	DRM_DEBUG("IRQ: uninst\n");
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
-	/* Disable PFIFO interrupts */
-	NV_WRITE(NV03_PFIFO_INTR_EN_0, 0);
-	/* Disable PGRAPH interrupts */
-	if (dev_priv->card_type<NV_40)
-		NV_WRITE(NV03_PGRAPH_INTR_EN, 0);
-	else
-		NV_WRITE(NV40_PGRAPH_INTR_EN, 0);
-#if 0
-	/* Disable CRTC0/1 interrupts */
-	NV_WRITE(NV_CRTC0_INTEN, 0);
-	NV_WRITE(NV_CRTC1_INTEN, 0);
-#endif
 	/* Master disable */
 	NV_WRITE(NV03_PMC_INTR_EN_0, 0);
 }
 
-static void nouveau_fifo_irq_handler(drm_device_t *dev)
+static void nouveau_fifo_irq_handler(struct drm_device *dev)
 {
 	uint32_t status, chmode, chstat, channel;
-	drm_nouveau_private_t *dev_priv = dev->dev_private;
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
 
 	status = NV_READ(NV03_PFIFO_INTR_0);
 	if (!status)
@@ -170,12 +72,10 @@ static void nouveau_fifo_irq_handler(drm_device_t *dev)
 	chstat = NV_READ(NV04_PFIFO_DMA);
 	channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
 
-	DRM_DEBUG("NV: PFIFO interrupt! Channel=%d, INTSTAT=0x%08x/MODE=0x%08x/PEND=0x%08x\n", channel, status, chmode, chstat);
-
 	if (status & NV_PFIFO_INTR_CACHE_ERROR) {
 		uint32_t c1get, c1method, c1data;
 
-		DRM_ERROR("NV: PFIFO error interrupt\n");
+		DRM_ERROR("PFIFO error interrupt\n");
 
 		c1get = NV_READ(NV03_PFIFO_CACHE1_GET) >> 2;
 		if (dev_priv->card_type < NV_40) {
@@ -187,17 +87,17 @@ static void nouveau_fifo_irq_handler(drm_device_t *dev)
 			c1data   = NV_READ(NV40_PFIFO_CACHE1_DATA(c1get));
 		}
 
-		DRM_ERROR("NV: Channel %d/%d - Method 0x%04x, Data 0x%08x\n",
-				channel, (c1method >> 13) & 7,
-				c1method & 0x1ffc, c1data
-			 );
+		DRM_ERROR("Channel %d/%d - Method 0x%04x, Data 0x%08x\n",
+			  channel, (c1method >> 13) & 7, c1method & 0x1ffc,
+			  c1data);
 
 		status &= ~NV_PFIFO_INTR_CACHE_ERROR;
 		NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
 	}
 
 	if (status & NV_PFIFO_INTR_DMA_PUSHER) {
-		DRM_INFO("NV: PFIFO DMA pusher interrupt\n");
+		DRM_ERROR("PFIFO DMA pusher interrupt: ch%d, 0x%08x\n",
+			  channel, NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
 
 		status &= ~NV_PFIFO_INTR_DMA_PUSHER;
 		NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_DMA_PUSHER);
@@ -211,7 +111,7 @@ static void nouveau_fifo_irq_handler(drm_device_t *dev)
 	}
 
 	if (status) {
-		DRM_INFO("NV: unknown PFIFO interrupt. status=0x%08x\n", status);
+		DRM_ERROR("Unhandled PFIFO interrupt: status=0x%08x\n", status);
 
 		NV_WRITE(NV03_PFIFO_INTR_0, status);
 	}
@@ -220,9 +120,9 @@ static void nouveau_fifo_irq_handler(drm_device_t *dev)
 }
 
 #if 0
-static void nouveau_nv04_context_switch(drm_device_t *dev)
+static void nouveau_nv04_context_switch(struct drm_device *dev)
 {
-	drm_nouveau_private_t *dev_priv = dev->dev_private;
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	uint32_t channel,i;
 	uint32_t max=0;
 	NV_WRITE(NV04_PGRAPH_FIFO,0x0);
@@ -266,95 +166,182 @@ static void nouveau_nv04_context_switch(drm_device_t *dev)
 }
 #endif
 
+
+struct nouveau_bitfield_names
+{
+	uint32_t mask;
+	const char * name;
+};
+
+static struct nouveau_bitfield_names nouveau_nstatus_names[] =
+{
+	{ NV03_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
+	{ NV03_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
+	{ NV03_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
+	{ NV03_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" }
+};
+
+static struct nouveau_bitfield_names nouveau_nsource_names[] =
+{
+	{ NV03_PGRAPH_NSOURCE_NOTIFICATION,       "NOTIFICATION" },
+	{ NV03_PGRAPH_NSOURCE_DATA_ERROR,         "DATA_ERROR" },
+	{ NV03_PGRAPH_NSOURCE_PROTECTION_ERROR,   "PROTECTION_ERROR" },
+	{ NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION,    "RANGE_EXCEPTION" },
+	{ NV03_PGRAPH_NSOURCE_LIMIT_COLOR,        "LIMIT_COLOR" },
+	{ NV03_PGRAPH_NSOURCE_LIMIT_ZETA,         "LIMIT_ZETA" },
+	{ NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD,       "ILLEGAL_MTHD" },
+	{ NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION,   "DMA_R_PROTECTION" },
+	{ NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION,   "DMA_W_PROTECTION" },
+	{ NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION,   "FORMAT_EXCEPTION" },
+	{ NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION,    "PATCH_EXCEPTION" },
+	{ NV03_PGRAPH_NSOURCE_STATE_INVALID,      "STATE_INVALID" },
+	{ NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY,      "DOUBLE_NOTIFY" },
+	{ NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE,      "NOTIFY_IN_USE" },
+	{ NV03_PGRAPH_NSOURCE_METHOD_CNT,         "METHOD_CNT" },
+	{ NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION,   "BFR_NOTIFICATION" },
+	{ NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
+	{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_A,        "DMA_WIDTH_A" },
+	{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_B,        "DMA_WIDTH_B" },
+};
+
 static void
-nouveau_graph_dump_trap_info(drm_device_t *dev)
+nouveau_print_bitfield_names(uint32_t value,
+                             const struct nouveau_bitfield_names *namelist,
+                             const int namelist_len)
 {
-	drm_nouveau_private_t *dev_priv = dev->dev_private;
+	int i;
+	for(i=0; i<namelist_len; ++i) {
+		uint32_t mask = namelist[i].mask;
+		if(value & mask) {
+			printk(" %s", namelist[i].name);
+			value &= ~mask;
+		}
+	}
+	if(value)
+		printk(" (unknown bits 0x%08x)", value);
+}
+
+static int
+nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
+{
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
+	int channel;
+
+	if (dev_priv->card_type < NV_10) {
+		channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf;
+	} else if (dev_priv->card_type < NV_40) {
+		channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
+	} else
+	if (dev_priv->card_type < NV_50) {
+		uint32_t cur_grctx = (NV_READ(0x40032C) & 0xfffff) << 4;
+
+		/* 0x400704 *sometimes* contains a sensible channel ID, but
+		 * mostly not.. for now lookup which channel owns the active
+		 * PGRAPH context.  Probably a better way, but this'll do
+		 * for now.
+		 */
+		for (channel = 0; channel < 32; channel++) {
+			if (dev_priv->fifos[channel] == NULL)
+				continue;
+			if (cur_grctx ==
+			    dev_priv->fifos[channel]->ramin_grctx->instance)
+				break;
+		}
+		if (channel == 32) {
+			DRM_ERROR("AIII, unable to determine active channel "
+				  "from PGRAPH context 0x%08x\n", cur_grctx);
+			return -EINVAL;
+		}
+	} else {
+		uint32_t cur_grctx = (NV_READ(0x40032C) & 0xfffff) << 12;
+
+		for (channel = 0; channel < 128; channel++) {
+			if (dev_priv->fifos[channel] == NULL)
+				continue;
+			if (cur_grctx ==
+			    dev_priv->fifos[channel]->ramin_grctx->instance)
+				break;
+		}
+		if (channel == 128) {
+			DRM_ERROR("AIII, unable to determine active channel "
+				  "from PGRAPH context 0x%08x\n", cur_grctx);
+			return -EINVAL;
+		}
+	}
+
+	if (channel > nouveau_fifo_number(dev) ||
+	    dev_priv->fifos[channel] == NULL) {
+		DRM_ERROR("AIII, invalid/inactive channel id %d\n", channel);
+		return -EINVAL;
+	}
+
+	*channel_ret = channel;
+	return 0;
+}
+
+static void
+nouveau_graph_dump_trap_info(struct drm_device *dev)
+{
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	uint32_t address;
-	uint32_t channel;
-	uint32_t method, subc, data;
+	uint32_t channel, class;
+	uint32_t method, subc, data, data2;
+	uint32_t nsource, nstatus;
 
-	address = NV_READ(0x400704);
-	data    = NV_READ(0x400708);
-	channel = (address >> 20) & 0x1F;
-	subc    = (address >> 16) & 0x7;
+	if (nouveau_graph_trapped_channel(dev, &channel))
+		channel = -1;
+
+	data    = NV_READ(NV04_PGRAPH_TRAPPED_DATA);
+	address = NV_READ(NV04_PGRAPH_TRAPPED_ADDR);
 	method  = address & 0x1FFC;
+	if (dev_priv->card_type < NV_10) {
+		subc = (address >> 13) & 0x7;
+		data2= 0;
+	} else {
+		subc = (address >> 16) & 0x7;
+		data2= NV_READ(NV10_PGRAPH_TRAPPED_DATA_HIGH);
+	}
+	nsource = NV_READ(NV03_PGRAPH_NSOURCE);
+	nstatus = NV_READ(NV03_PGRAPH_NSTATUS);
+	if (dev_priv->card_type < NV_50) {
+		class = NV_READ(0x400160 + subc*4) & 0xFFFF;
+	} else {
+		class = NV_READ(0x400814);
+	}
 
-	DRM_ERROR("NV: nSource: 0x%08x, nStatus: 0x%08x\n",
-			NV_READ(0x400108), NV_READ(0x400104));
-	DRM_ERROR("NV: Channel %d/%d (class 0x%04x) -"
-			"Method 0x%04x, Data 0x%08x\n",
-			channel, subc,
-			NV_READ(0x400160+subc*4) & 0xFFFF,
-			method, data
-		 );
+	DRM_ERROR("nSource:");
+	nouveau_print_bitfield_names(nsource, nouveau_nsource_names,
+	                             ARRAY_SIZE(nouveau_nsource_names));
+	printk(", nStatus:");
+	nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names,
+	                             ARRAY_SIZE(nouveau_nstatus_names));
+	printk("\n");
+
+	DRM_ERROR("Channel %d/%d (class 0x%04x) - Method 0x%04x, Data 0x%08x:0x%08x\n",
+		  channel, subc, class, method, data2, data);
 }
 
-static void nouveau_pgraph_irq_handler(drm_device_t *dev)
+static void nouveau_pgraph_irq_handler(struct drm_device *dev)
 {
-	uint32_t status;
-	drm_nouveau_private_t *dev_priv = dev->dev_private;
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
+	uint32_t status, nsource;
 
 	status = NV_READ(NV03_PGRAPH_INTR);
 	if (!status)
 		return;
+	nsource = NV_READ(NV03_PGRAPH_NSOURCE);
 
 	if (status & NV_PGRAPH_INTR_NOTIFY) {
-		uint32_t nsource, nstatus, instance, notify;
-		DRM_DEBUG("NV: PGRAPH notify interrupt\n");
+		DRM_DEBUG("PGRAPH notify interrupt\n");
 
-		nstatus = NV_READ(0x00400104);
-		nsource = NV_READ(0x00400108);
-		DRM_DEBUG("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus);
-
-		/* if this wasn't NOTIFICATION_PENDING, dump extra trap info */
-		if (nsource & ~(1<<0)) {
-			nouveau_graph_dump_trap_info(dev);
-		} else {
-			instance = NV_READ(0x00400158);
-			notify   = NV_READ(0x00400150) >> 16;
-			DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n",
-					nsource, nstatus);
-		}
+		nouveau_graph_dump_trap_info(dev);
 
 		status &= ~NV_PGRAPH_INTR_NOTIFY;
 		NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
 	}
 
-	if (status & NV_PGRAPH_INTR_BUFFER_NOTIFY) {
-		uint32_t nsource, nstatus, instance, notify;
-		DRM_DEBUG("NV: PGRAPH buffer notify interrupt\n");
-
-		nstatus = NV_READ(0x00400104);
-		nsource = NV_READ(0x00400108);
-		DRM_DEBUG("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus);
-
-		instance = NV_READ(0x00400158);
-		notify   = NV_READ(0x00400150) >> 16;
-		DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n", instance, notify);
-
-		status &= ~NV_PGRAPH_INTR_BUFFER_NOTIFY;
-		NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_BUFFER_NOTIFY);
-	}
-
-	if (status & NV_PGRAPH_INTR_MISSING_HW) {
-		DRM_ERROR("NV: PGRAPH missing hw interrupt\n");
-
-		status &= ~NV_PGRAPH_INTR_MISSING_HW;
-		NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_MISSING_HW);
-	}
-
 	if (status & NV_PGRAPH_INTR_ERROR) {
-		uint32_t nsource, nstatus, instance;
-
-		DRM_ERROR("NV: PGRAPH error interrupt\n");
-
-		nstatus = NV_READ(0x00400104);
-		nsource = NV_READ(0x00400108);
-		DRM_ERROR("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus);
-
-		instance = NV_READ(0x00400158);
-		DRM_ERROR("instance:0x%08x\n", instance);
+		DRM_ERROR("PGRAPH error interrupt\n");
 
 		nouveau_graph_dump_trap_info(dev);
 
@@ -364,7 +351,7 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev)
 
 	if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
 		uint32_t channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
-		DRM_INFO("NV: PGRAPH context switch interrupt channel %x\n",channel);
+		DRM_DEBUG("PGRAPH context switch interrupt channel %x\n",channel);
 		switch(dev_priv->card_type)
 		{
 			case NV_04:
@@ -372,6 +359,7 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev)
 				nouveau_nv04_context_switch(dev);
 				break;
 			case NV_10:
+			case NV_11:
 			case NV_17:
 				nouveau_nv10_context_switch(dev);
 				break;
@@ -380,7 +368,7 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev)
 				nouveau_nv20_context_switch(dev);
 				break;
 			default:
-				DRM_INFO("NV: Context switch not implemented\n");
+				DRM_ERROR("Context switch not implemented\n");
 				break;
 		}
 
@@ -389,16 +377,17 @@ static void nouveau_pgraph_irq_handler(drm_device_t *dev)
 	}
 
 	if (status) {
-		DRM_INFO("NV: Unknown PGRAPH interrupt! STAT=0x%08x\n", status);
+		DRM_ERROR("Unhandled PGRAPH interrupt: STAT=0x%08x\n", status);
 		NV_WRITE(NV03_PGRAPH_INTR, status);
 	}
 
 	NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
 }
 
-static void nouveau_crtc_irq_handler(drm_device_t *dev, int crtc)
+static void nouveau_crtc_irq_handler(struct drm_device *dev, int crtc)
 {
-	drm_nouveau_private_t *dev_priv = dev->dev_private;
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
+
 	if (crtc&1) {
 		NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
 	}
@@ -410,24 +399,24 @@ static void nouveau_crtc_irq_handler(drm_device_t *dev, int crtc)
 
 irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS)
 {
-	drm_device_t          *dev = (drm_device_t*)arg;
-	drm_nouveau_private_t *dev_priv = dev->dev_private;
+	struct drm_device *dev = (struct drm_device*)arg;
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
 	uint32_t status;
 
 	status = NV_READ(NV03_PMC_INTR_0);
 	if (!status)
 		return IRQ_NONE;
 
-	DRM_DEBUG("PMC INTSTAT: 0x%08x\n", status);
-
 	if (status & NV_PMC_INTR_0_PFIFO_PENDING) {
 		nouveau_fifo_irq_handler(dev);
 		status &= ~NV_PMC_INTR_0_PFIFO_PENDING;
 	}
+
 	if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
 		nouveau_pgraph_irq_handler(dev);
 		status &= ~NV_PMC_INTR_0_PGRAPH_PENDING;
 	}
+
 	if (status & NV_PMC_INTR_0_CRTCn_PENDING) {
 		nouveau_crtc_irq_handler(dev, (status>>24)&3);
 		status &= ~NV_PMC_INTR_0_CRTCn_PENDING;