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-rw-r--r--shared-core/nouveau_drm.h123
-rw-r--r--shared-core/nouveau_drv.h2
-rw-r--r--shared-core/nouveau_mem.c11
-rw-r--r--shared-core/nouveau_state.c9
4 files changed, 136 insertions, 9 deletions
diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h
index a99c6156..4147f357 100644
--- a/shared-core/nouveau_drm.h
+++ b/shared-core/nouveau_drm.h
@@ -25,13 +25,26 @@
#ifndef __NOUVEAU_DRM_H__
#define __NOUVEAU_DRM_H__
-#define NOUVEAU_DRM_HEADER_PATCHLEVEL 11
+#define NOUVEAU_DRM_HEADER_PATCHLEVEL 12
struct drm_nouveau_channel_alloc {
uint32_t fb_ctxdma_handle;
uint32_t tt_ctxdma_handle;
int channel;
+
+ /* Notifier memory */
+ drm_handle_t notifier;
+ int notifier_size;
+
+ /* DRM-enforced subchannel assignments */
+ struct {
+ uint32_t handle;
+ uint32_t grclass;
+ } subchan[8];
+ uint32_t nr_subchan;
+
+/* !MM_ENABLED ONLY */
uint32_t put_base;
/* FIFO control regs */
drm_handle_t ctrl;
@@ -39,9 +52,6 @@ struct drm_nouveau_channel_alloc {
/* DMA command buffer */
drm_handle_t cmdbuf;
int cmdbuf_size;
- /* Notifier memory */
- drm_handle_t notifier;
- int notifier_size;
};
struct drm_nouveau_channel_free {
@@ -126,6 +136,8 @@ struct drm_nouveau_mem_tile {
#define NOUVEAU_GETPARAM_AGP_SIZE 9
#define NOUVEAU_GETPARAM_PCI_PHYSICAL 10
#define NOUVEAU_GETPARAM_CHIPSET_ID 11
+#define NOUVEAU_GETPARAM_MM_ENABLED 12
+#define NOUVEAU_GETPARAM_VM_VRAM_BASE 13
struct drm_nouveau_getparam {
uint64_t param;
uint64_t value;
@@ -138,6 +150,100 @@ struct drm_nouveau_setparam {
uint64_t value;
};
+#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
+#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
+#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
+#define NOUVEAU_GEM_DOMAIN_NOMAP (1 << 3)
+#define NOUVEAU_GEM_DOMAIN_TILE (1 << 30)
+#define NOUVEAU_GEM_DOMAIN_TILE_ZETA (1 << 31)
+
+struct drm_nouveau_gem_new {
+ uint64_t size;
+ uint32_t channel_hint;
+ uint32_t align;
+ uint32_t handle;
+ uint32_t domain;
+ uint32_t offset;
+};
+
+struct drm_nouveau_gem_pushbuf_bo {
+ uint64_t user_priv;
+ uint32_t handle;
+ uint32_t read_domains;
+ uint32_t write_domains;
+ uint32_t valid_domains;
+ uint32_t presumed_ok;
+ uint32_t presumed_domain;
+ uint64_t presumed_offset;
+};
+
+#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
+#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
+#define NOUVEAU_GEM_RELOC_OR (1 << 2)
+struct drm_nouveau_gem_pushbuf_reloc {
+ uint32_t bo_index;
+ uint32_t reloc_index;
+ uint32_t flags;
+ uint32_t data;
+ uint32_t vor;
+ uint32_t tor;
+};
+
+#define NOUVEAU_GEM_MAX_BUFFERS 1024
+#define NOUVEAU_GEM_MAX_RELOCS 1024
+
+struct drm_nouveau_gem_pushbuf {
+ uint32_t channel;
+ uint32_t nr_dwords;
+ uint32_t nr_buffers;
+ uint32_t nr_relocs;
+ uint64_t dwords;
+ uint64_t buffers;
+ uint64_t relocs;
+};
+
+struct drm_nouveau_gem_pushbuf_call {
+ uint32_t channel;
+ uint32_t handle;
+ uint32_t offset;
+ uint32_t nr_buffers;
+ uint32_t nr_relocs;
+ uint32_t pad0;
+ uint64_t buffers;
+ uint64_t relocs;
+};
+
+struct drm_nouveau_gem_pin {
+ uint32_t handle;
+ uint32_t domain;
+ uint64_t offset;
+};
+
+struct drm_nouveau_gem_unpin {
+ uint32_t handle;
+};
+
+struct drm_nouveau_gem_mmap {
+ uint32_t handle;
+ uint32_t pad;
+ uint64_t vaddr;
+};
+
+struct drm_nouveau_gem_cpu_prep {
+ uint32_t handle;
+};
+
+struct drm_nouveau_gem_cpu_fini {
+ uint32_t handle;
+};
+
+struct drm_nouveau_gem_tile {
+ uint32_t handle;
+ uint32_t delta;
+ uint32_t size;
+ uint32_t flags;
+};
+
enum nouveau_card_type {
NV_UNKNOWN =0,
NV_04 =4,
@@ -180,5 +286,14 @@ struct drm_nouveau_sarea {
#define DRM_NOUVEAU_MEM_TILE 0x0a
#define DRM_NOUVEAU_SUSPEND 0x0b
#define DRM_NOUVEAU_RESUME 0x0c
+#define DRM_NOUVEAU_GEM_NEW 0x40
+#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
+#define DRM_NOUVEAU_GEM_PUSHBUF_CALL 0x42
+#define DRM_NOUVEAU_GEM_PIN 0x43
+#define DRM_NOUVEAU_GEM_UNPIN 0x44
+#define DRM_NOUVEAU_GEM_MMAP 0x45
+#define DRM_NOUVEAU_GEM_CPU_PREP 0x46
+#define DRM_NOUVEAU_GEM_CPU_FINI 0x47
+#define DRM_NOUVEAU_GEM_TILE 0x48
#endif /* __NOUVEAU_DRM_H__ */
diff --git a/shared-core/nouveau_drv.h b/shared-core/nouveau_drv.h
index a97e3e99..158d6fde 100644
--- a/shared-core/nouveau_drv.h
+++ b/shared-core/nouveau_drv.h
@@ -34,7 +34,7 @@
#define DRIVER_MAJOR 0
#define DRIVER_MINOR 0
-#define DRIVER_PATCHLEVEL 11
+#define DRIVER_PATCHLEVEL 12
#define NOUVEAU_FAMILY 0x0000FFFF
#define NOUVEAU_FLAGS 0xFFFF0000
diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c
index d79c1a52..0d590276 100644
--- a/shared-core/nouveau_mem.c
+++ b/shared-core/nouveau_mem.c
@@ -587,18 +587,21 @@ nouveau_mem_alloc(struct drm_device *dev, int alignment, uint64_t size,
* Make things easier on ourselves: all allocations are page-aligned.
* We need that to map allocated regions into the user space
*/
- if (alignment < PAGE_SHIFT)
- alignment = PAGE_SHIFT;
+ if (alignment < PAGE_SIZE)
+ alignment = PAGE_SIZE;
/* Align allocation sizes to 64KiB blocks on G8x. We use a 64KiB
* page size in the GPU VM.
*/
if (flags & NOUVEAU_MEM_FB && dev_priv->card_type >= NV_50) {
size = (size + 65535) & ~65535;
- if (alignment < 16)
- alignment = 16;
+ if (alignment < 65536)
+ alignment = 65536;
}
+ /* Further down wants alignment in pages, not bytes */
+ alignment >>= PAGE_SHIFT;
+
/*
* Warn about 0 sized allocations, but let it go through. It'll return 1 page
*/
diff --git a/shared-core/nouveau_state.c b/shared-core/nouveau_state.c
index 4e0140a5..0b6002ce 100644
--- a/shared-core/nouveau_state.c
+++ b/shared-core/nouveau_state.c
@@ -630,6 +630,15 @@ int nouveau_ioctl_getparam(struct drm_device *dev, void *data, struct drm_file *
case NOUVEAU_GETPARAM_AGP_SIZE:
getparam->value=dev_priv->gart_info.aper_size;
break;
+ case NOUVEAU_GETPARAM_MM_ENABLED:
+ getparam->value = 0;
+ break;
+ case NOUVEAU_GETPARAM_VM_VRAM_BASE:
+ if (dev_priv->card_type >= NV_50)
+ getparam->value = 0x20000000;
+ else
+ getparam->value = 0;
+ break;
default:
DRM_ERROR("unknown parameter %lld\n", getparam->param);
return -EINVAL;
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 18:01:55 +0000