radeon_ms: rework command submission ioctl & cleanup

11 files changed, 436 insertions, 333 deletions

diff --git a/shared-core/amd.h b/shared-core/amd.h
index 31cf3eff..f8096053 100644
--- a/shared-core/amd.h
+++ b/shared-core/amd.h
@@ -31,38 +31,55 @@
  * around during command validation (ie check that user have the right to
  * execute the given command).
  */
-struct amd_cbuffer_arg
+struct amd_cmd_bo
 {
-	struct list_head         list;
-	struct drm_buffer_object *buffer;
-	int32_t                  dw_id;
+	struct list_head            list;
+	uint64_t                    *offsets;
+	uint32_t                    *cdw_id;
+	struct drm_buffer_object    *bo;
+	unsigned int                handle;
+	uint64_t                    mask;
+	uint64_t                    flags;
+	uint32_t                    type;
 };
 
-struct amd_cbuffer
+struct amd_cmd
 {
-	uint32_t                 *cbuffer;
-	uint32_t                 cbuffer_dw_count;
-	struct amd_cbuffer_arg   arg_unused;
-	struct amd_cbuffer_arg   arg_used;
-	struct amd_cbuffer_arg   *args;
-	void			 *driver;
+	uint32_t                    *cdw;
+	uint32_t                    cdw_count;
+	struct drm_bo_kmap_obj      cdw_kmap;
+	size_t                      cdw_size;
+	struct amd_cmd_bo           *cdw_bo;
+	struct amd_cmd_bo           bo_unused;
+	struct amd_cmd_bo           bo_used;
+	struct amd_cmd_bo           *bo;
+	uint32_t                    bo_count;
+	void                        *driver;
 };
 
-struct amd_cbuffer_checker
+struct amd_cmd_module
 {
 	uint32_t numof_p0_checkers;
 	uint32_t numof_p3_checkers;
-	int (*check)(struct drm_device *dev, struct amd_cbuffer *cbuffer);
-	int (**check_p0)(struct drm_device *dev, struct amd_cbuffer *cbuffer,
-			 int dw_id, int reg);
-	int (**check_p3)(struct drm_device *dev, struct amd_cbuffer *cbuffer,
-			 int dw_id, int op, int count);
+	int (*check)(struct drm_device *dev, struct amd_cmd *cmd);
+	int (**check_p0)(struct drm_device *dev, struct amd_cmd *cmd,
+			 int cdw_id, int reg);
+	int (**check_p3)(struct drm_device *dev, struct amd_cmd *cmd,
+			 int cdw_id, int op, int count);
 };
 
-struct amd_cbuffer_arg *
-amd_cbuffer_arg_from_dw_id(struct amd_cbuffer_arg *head, uint32_t dw_id);
-int amd_cbuffer_check(struct drm_device *dev, struct amd_cbuffer *cbuffer);
+int amd_cmd_check(struct drm_device *dev, struct amd_cmd *cmd);
+int amd_ioctl_cmd(struct drm_device *dev, void *data, struct drm_file *file);
 
+static inline struct amd_cmd_bo *amd_cmd_get_bo(struct amd_cmd *cmd, int i)
+{
+	if (i < cmd->bo_count && cmd->bo[i].type == DRM_AMD_CMD_BO_TYPE_DATA) {
+		list_del(&cmd->bo[i].list);
+		list_add_tail(&cmd->bo[i].list, &cmd->bo_used.list);
+		return &cmd->bo[i]; 
+	}
+	return NULL;
+}
 
 /* struct amd_fb amd is for storing amd framebuffer informations
  */
diff --git a/shared-core/amd_legacy.h b/shared-core/amd_legacy.h
index 92997dcd..c1e5f5da 100644
--- a/shared-core/amd_legacy.h
+++ b/shared-core/amd_legacy.h
@@ -27,7 +27,7 @@
 #ifndef __AMD_LEGACY_H__
 #define __AMD_LEGACY_H__
 
-int amd_legacy_cbuffer_destroy(struct drm_device *dev);
-int amd_legacy_cbuffer_initialize(struct drm_device *dev);
+int amd_legacy_cmd_module_destroy(struct drm_device *dev);
+int amd_legacy_cmd_module_initialize(struct drm_device *dev);
 
 #endif
diff --git a/shared-core/amd_legacy_cbuffer.c b/shared-core/amd_legacy_cbuffer.c
index f1b7a44b..7971ee67 100644
--- a/shared-core/amd_legacy_cbuffer.c
+++ b/shared-core/amd_legacy_cbuffer.c
@@ -44,23 +44,23 @@ struct legacy_check
 	uint32_t                dp_gui_master_cntl;
 	uint32_t                dst_offset;
 	uint32_t                dst_pitch;
-	struct amd_cbuffer_arg  *dst;
+	struct amd_cmd_bo       *dst;
 	uint32_t                dst_x;
 	uint32_t                dst_y;
 	uint32_t                dst_h;
 	uint32_t                dst_w;
-	struct amd_cbuffer_arg  *src;
+	struct amd_cmd_bo       *src;
 	uint32_t                src_pitch;
 	uint32_t                src_x;
 	uint32_t                src_y;
 };
 
-static int check_blit(struct drm_device *dev, struct amd_cbuffer *cbuffer)
+static int check_blit(struct drm_device *dev, struct amd_cmd *cmd)
 {
 	struct legacy_check *legacy_check;
 	long bpp, start, end;
 	
-	legacy_check = (struct legacy_check *)cbuffer->driver;
+	legacy_check = (struct legacy_check *)cmd->driver;
 	/* check that gui master cntl have been set */
 	if (legacy_check->dp_gui_master_cntl == 0xffffffff) {
 		return -EINVAL;
@@ -132,13 +132,13 @@ static int check_blit(struct drm_device *dev, struct amd_cbuffer *cbuffer)
 }
 
 static int p0_dp_gui_master_cntl(struct drm_device *dev,
-				 struct amd_cbuffer *cbuffer,
-				 int dw_id, int reg)
+				 struct amd_cmd *cmd,
+				 int cdw_id, int reg)
 {
 	struct legacy_check *legacy_check;
 	
-	legacy_check = (struct legacy_check *)cbuffer->driver;
-	legacy_check->dp_gui_master_cntl = cbuffer->cbuffer[dw_id];
+	legacy_check = (struct legacy_check *)cmd->driver;
+	legacy_check->dp_gui_master_cntl = cmd->cdw[cdw_id];
 	/* we only accept src data type to be same as dst */
 	if (((legacy_check->dp_gui_master_cntl >> 12) & 0x3) != 3) {
 		return -EINVAL;
@@ -147,125 +147,139 @@ static int p0_dp_gui_master_cntl(struct drm_device *dev,
 }
 
 static int p0_dst_pitch_offset(struct drm_device *dev,
-			       struct amd_cbuffer *cbuffer,
-			       int dw_id, int reg)
+			       struct amd_cmd *cmd,
+			       int cdw_id, int reg)
 {
 	struct legacy_check *legacy_check;
-	uint32_t gpu_addr;
+	uint32_t tmp;
 	int ret;
 	
-	legacy_check = (struct legacy_check *)cbuffer->driver;
-	legacy_check->dst_pitch = ((cbuffer->cbuffer[dw_id] >> 22) & 0xff) << 6;
-	legacy_check->dst = amd_cbuffer_arg_from_dw_id(&cbuffer->arg_unused,
-						       dw_id);
+	legacy_check = (struct legacy_check *)cmd->driver;
+	legacy_check->dst_pitch = ((cmd->cdw[cdw_id] >> 22) & 0xff) << 6;
+	tmp = cmd->cdw[cdw_id] & 0x003fffff;
+	legacy_check->dst = amd_cmd_get_bo(cmd, tmp);
 	if (legacy_check->dst == NULL) {
+		DRM_ERROR("invalid bo (%d) for DST_PITCH_OFFSET register.\n",
+			  tmp);
 		return -EINVAL;
 	}
-	ret = radeon_ms_bo_get_gpu_addr(dev, &legacy_check->dst->buffer->mem,
-					&gpu_addr);
+	ret = radeon_ms_bo_get_gpu_addr(dev, &legacy_check->dst->bo->mem, &tmp);
 	if (ret) {
+		DRM_ERROR("failed to get GPU offset for bo 0x%x.\n",
+			  legacy_check->dst->handle);
 		return -EINVAL;
 	}
-	cbuffer->cbuffer[dw_id] &= 0xffc00000;
-	cbuffer->cbuffer[dw_id] |= (gpu_addr >> 10);
+	if (tmp & 0x3fff) {
+		DRM_ERROR("bo 0x%x offset doesn't meet alignement 0x%x.\n",
+			  legacy_check->dst->handle, tmp);
+	}
+	cmd->cdw[cdw_id] &= 0xffc00000;
+	cmd->cdw[cdw_id] |= (tmp >> 10);
 	return 0;
 }
 
 static int p0_src_pitch_offset(struct drm_device *dev,
-			       struct amd_cbuffer *cbuffer,
-			       int dw_id, int reg)
+			       struct amd_cmd *cmd,
+			       int cdw_id, int reg)
 {
 	struct legacy_check *legacy_check;
-	uint32_t gpu_addr;
+	uint32_t tmp;
 	int ret;
 	
-	legacy_check = (struct legacy_check *)cbuffer->driver;
-	legacy_check->src_pitch = ((cbuffer->cbuffer[dw_id] >> 22) & 0xff) << 6;
-	legacy_check->src = amd_cbuffer_arg_from_dw_id(&cbuffer->arg_unused,
-						       dw_id);
-	if (legacy_check->dst == NULL) {
+	legacy_check = (struct legacy_check *)cmd->driver;
+	legacy_check->src_pitch = ((cmd->cdw[cdw_id] >> 22) & 0xff) << 6;
+	tmp = cmd->cdw[cdw_id] & 0x003fffff;
+	legacy_check->src = amd_cmd_get_bo(cmd, tmp);
+	if (legacy_check->src == NULL) {
+		DRM_ERROR("invalid bo (%d) for SRC_PITCH_OFFSET register.\n",
+			  tmp);
 		return -EINVAL;
 	}
-	ret = radeon_ms_bo_get_gpu_addr(dev, &legacy_check->src->buffer->mem,
-					&gpu_addr);
+	ret = radeon_ms_bo_get_gpu_addr(dev, &legacy_check->src->bo->mem, &tmp);
 	if (ret) {
+		DRM_ERROR("failed to get GPU offset for bo 0x%x.\n",
+			  legacy_check->src->handle);
 		return -EINVAL;
 	}
-	cbuffer->cbuffer[dw_id] &= 0xffc00000;
-	cbuffer->cbuffer[dw_id] |= (gpu_addr >> 10);
+	if (tmp & 0x3fff) {
+		DRM_ERROR("bo 0x%x offset doesn't meet alignement 0x%x.\n",
+			  legacy_check->src->handle, tmp);
+	}
+	cmd->cdw[cdw_id] &= 0xffc00000;
+	cmd->cdw[cdw_id] |= (tmp >> 10);
 	return 0;
 }
 
 static int p0_dst_y_x(struct drm_device *dev,
-		      struct amd_cbuffer *cbuffer,
-		      int dw_id, int reg)
+		      struct amd_cmd *cmd,
+		      int cdw_id, int reg)
 {
 	struct legacy_check *legacy_check;
 	
-	legacy_check = (struct legacy_check *)cbuffer->driver;
-	legacy_check->dst_x = cbuffer->cbuffer[dw_id] & 0xffff;
-	legacy_check->dst_y = (cbuffer->cbuffer[dw_id] >> 16) & 0xffff;
+	legacy_check = (struct legacy_check *)cmd->driver;
+	legacy_check->dst_x = cmd->cdw[cdw_id] & 0xffff;
+	legacy_check->dst_y = (cmd->cdw[cdw_id] >> 16) & 0xffff;
 	return 0;
 }
 
 static int p0_src_y_x(struct drm_device *dev,
-		      struct amd_cbuffer *cbuffer,
-		      int dw_id, int reg)
+		      struct amd_cmd *cmd,
+		      int cdw_id, int reg)
 {
 	struct legacy_check *legacy_check;
 	
-	legacy_check = (struct legacy_check *)cbuffer->driver;
-	legacy_check->src_x = cbuffer->cbuffer[dw_id] & 0xffff;
-	legacy_check->src_y = (cbuffer->cbuffer[dw_id] >> 16) & 0xffff;
+	legacy_check = (struct legacy_check *)cmd->driver;
+	legacy_check->src_x = cmd->cdw[cdw_id] & 0xffff;
+	legacy_check->src_y = (cmd->cdw[cdw_id] >> 16) & 0xffff;
 	return 0;
 }
 
 static int p0_dst_h_w(struct drm_device *dev,
-		      struct amd_cbuffer *cbuffer,
-		      int dw_id, int reg)
+		      struct amd_cmd *cmd,
+		      int cdw_id, int reg)
 {
 	struct legacy_check *legacy_check;
 	
-	legacy_check = (struct legacy_check *)cbuffer->driver;
-	legacy_check->dst_w = cbuffer->cbuffer[dw_id] & 0xffff;
-	legacy_check->dst_h = (cbuffer->cbuffer[dw_id] >> 16) & 0xffff;
-	return check_blit(dev, cbuffer);
+	legacy_check = (struct legacy_check *)cmd->driver;
+	legacy_check->dst_w = cmd->cdw[cdw_id] & 0xffff;
+	legacy_check->dst_h = (cmd->cdw[cdw_id] >> 16) & 0xffff;
+	return check_blit(dev, cmd);
 }
 
-static int legacy_cbuffer_check(struct drm_device *dev,
-				struct amd_cbuffer *cbuffer)
+static int legacy_cmd_check(struct drm_device *dev,
+				struct amd_cmd *cmd)
 {
 	struct legacy_check legacy_check;
 
 	memset(&legacy_check, 0xff, sizeof(struct legacy_check));
-	cbuffer->driver = &legacy_check;
-	return amd_cbuffer_check(dev, cbuffer);
+	cmd->driver = &legacy_check;
+	return amd_cmd_check(dev, cmd);
 }
 
-int amd_legacy_cbuffer_destroy(struct drm_device *dev)
+int amd_legacy_cmd_module_destroy(struct drm_device *dev)
 {
 	struct drm_radeon_private *dev_priv = dev->dev_private;
 
-	dev_priv->cbuffer_checker.check = NULL;
-	if (dev_priv->cbuffer_checker.numof_p0_checkers) {
-		drm_free(dev_priv->cbuffer_checker.check_p0,
-			 dev_priv->cbuffer_checker.numof_p0_checkers *
+	dev_priv->cmd_module.check = NULL;
+	if (dev_priv->cmd_module.numof_p0_checkers) {
+		drm_free(dev_priv->cmd_module.check_p0,
+			 dev_priv->cmd_module.numof_p0_checkers *
 			 sizeof(void*), DRM_MEM_DRIVER);
-		dev_priv->cbuffer_checker.numof_p0_checkers = 0;
+		dev_priv->cmd_module.numof_p0_checkers = 0;
 	}
-	if (dev_priv->cbuffer_checker.numof_p3_checkers) {
-		drm_free(dev_priv->cbuffer_checker.check_p3,
-			 dev_priv->cbuffer_checker.numof_p3_checkers *
+	if (dev_priv->cmd_module.numof_p3_checkers) {
+		drm_free(dev_priv->cmd_module.check_p3,
+			 dev_priv->cmd_module.numof_p3_checkers *
 			 sizeof(void*), DRM_MEM_DRIVER);
-		dev_priv->cbuffer_checker.numof_p3_checkers = 0;
+		dev_priv->cmd_module.numof_p3_checkers = 0;
 	}
 	return 0;
 }
 
-int amd_legacy_cbuffer_initialize(struct drm_device *dev)
+int amd_legacy_cmd_module_initialize(struct drm_device *dev)
 {
 	struct drm_radeon_private *dev_priv = dev->dev_private;
-	struct amd_cbuffer_checker *checker = &dev_priv->cbuffer_checker;
+	struct amd_cmd_module *checker = &dev_priv->cmd_module;
 	long size;
 
 	/* packet 0 */
@@ -273,7 +287,7 @@ int amd_legacy_cbuffer_initialize(struct drm_device *dev)
 	size = checker->numof_p0_checkers * sizeof(void*);
 	checker->check_p0 = drm_alloc(size, DRM_MEM_DRIVER);
 	if (checker->check_p0 == NULL) {
-		amd_legacy_cbuffer_destroy(dev);
+		amd_legacy_cmd_module_destroy(dev);
 		return -ENOMEM;
 	}
 	/* initialize to -1 */
@@ -284,7 +298,7 @@ int amd_legacy_cbuffer_initialize(struct drm_device *dev)
 	size = checker->numof_p3_checkers * sizeof(void*);
 	checker->check_p3 = drm_alloc(size, DRM_MEM_DRIVER);
 	if (checker->check_p3 == NULL) {
-		amd_legacy_cbuffer_destroy(dev);
+		amd_legacy_cmd_module_destroy(dev);
 		return -ENOMEM;
 	}
 	/* initialize to -1 */
@@ -301,6 +315,6 @@ int amd_legacy_cbuffer_initialize(struct drm_device *dev)
 	checker->check_p0[RADEON_DP_WRITE_MASK >> 2] = NULL;
 	checker->check_p0[RADEON_DP_CNTL >> 2] = NULL;
 
-	checker->check = legacy_cbuffer_check;
+	checker->check = legacy_cmd_check;
 	return 0;
 }
diff --git a/shared-core/radeon_ms.h b/shared-core/radeon_ms.h
index ec264207..dd34683e 100644
--- a/shared-core/radeon_ms.h
+++ b/shared-core/radeon_ms.h
@@ -330,7 +330,7 @@ struct drm_radeon_private {
 	uint8_t                     bus_ready;
 	uint8_t                     write_back;
 	/* command buffer informations */
-	struct amd_cbuffer_checker  cbuffer_checker;
+	struct amd_cmd_module       cmd_module;
 	/* abstract asic specific structures */
 	struct radeon_ms_rom        rom;
 	struct radeon_ms_properties properties;
@@ -426,10 +426,6 @@ int radeon_ms_driver_load(struct drm_device *dev, unsigned long flags);
 int radeon_ms_driver_open(struct drm_device * dev, struct drm_file *file_priv);
 int radeon_ms_driver_unload(struct drm_device *dev);
 
-/* radeon_ms_exec.c */
-int radeon_ms_execbuffer(struct drm_device *dev, void *data,
-			 struct drm_file *file_priv);
-
 /* radeon_ms_family.c */
 int radeon_ms_family_init(struct drm_device *dev);
 
diff --git a/shared-core/radeon_ms_bo.c b/shared-core/radeon_ms_bo.c
index 015595a4..b366ae5a 100644
--- a/shared-core/radeon_ms_bo.c
+++ b/shared-core/radeon_ms_bo.c
@@ -134,8 +134,9 @@ static int radeon_ms_bo_move_blit(struct drm_buffer_object *bo,
 	
 	ret = drm_bo_move_accel_cleanup(bo, evict, no_wait, 0,
 					 DRM_FENCE_TYPE_EXE |
-					 DRM_RADEON_FENCE_TYPE_RW,
-					 DRM_RADEON_FENCE_FLAG_FLUSHED,
+					 DRM_AMD_FENCE_TYPE_R |
+					 DRM_AMD_FENCE_TYPE_W,
+					 DRM_AMD_FENCE_FLAG_FLUSH,
 					 new_mem);
 	return ret;
 }
diff --git a/shared-core/radeon_ms_cp.c b/shared-core/radeon_ms_cp.c
index f551000a..3ddeea47 100644
--- a/shared-core/radeon_ms_cp.c
+++ b/shared-core/radeon_ms_cp.c
@@ -332,7 +332,7 @@ int radeon_ms_ring_emit(struct drm_device *dev, uint32_t *cmd, uint32_t count)
 	dev_priv->ring_free -= count;
 	for (i = 0; i < count; i++) {
 		dev_priv->ring_buffer[dev_priv->ring_wptr] = cmd[i];
-		DRM_INFO("ring[%d]=0x%08X\n", dev_priv->ring_wptr, cmd[i]);
+		DRM_DEBUG("ring[%d]=0x%08X\n", dev_priv->ring_wptr, cmd[i]);
 		dev_priv->ring_wptr++;
 		dev_priv->ring_wptr &= dev_priv->ring_mask;
 	}
diff --git a/shared-core/radeon_ms_crtc.c b/shared-core/radeon_ms_crtc.c
index 83dd0777..3586e019 100644
--- a/shared-core/radeon_ms_crtc.c
+++ b/shared-core/radeon_ms_crtc.c
@@ -551,6 +551,7 @@ static void radeon_ms_crtc1_mode_set(struct drm_crtc *crtc,
 			format = 4;
 		}
 		break;
+	case 24:
 	case 32:
 		format = 6;
 		break;
@@ -648,7 +649,7 @@ static void radeon_ms_crtc1_mode_set_base(struct drm_crtc *crtc, int x, int y)
 	struct drm_radeon_private *dev_priv = dev->dev_private;
 	struct radeon_state *state = &dev_priv->driver_state;
 
-	DRM_INFO("[radeon_ms] mode_set_base\n");
+	DRM_INFO("mode_set_base 0x%lX\n", crtc->fb->bo->offset);
 	state->crtc_offset = REG_S(CRTC_OFFSET, CRTC_OFFSET, crtc->fb->bo->offset);
 	radeon_ms_crtc1_restore(dev, state);
 }
diff --git a/shared-core/radeon_ms_drm.c b/shared-core/radeon_ms_drm.c
index 0d327925..9238de24 100644
--- a/shared-core/radeon_ms_drm.c
+++ b/shared-core/radeon_ms_drm.c
@@ -59,8 +59,8 @@ struct drm_bo_driver radeon_ms_bo_driver = {
 };
 
 struct drm_ioctl_desc radeon_ms_ioctls[] = {
-	DRM_IOCTL_DEF(DRM_RADEON_EXECBUFFER, radeon_ms_execbuffer, DRM_AUTH),
-	DRM_IOCTL_DEF(DRM_RADEON_RESETCP, radeon_ms_resetcp, DRM_AUTH),
+	DRM_IOCTL_DEF(DRM_AMD_CMD, amd_ioctl_cmd, DRM_AUTH),
+	DRM_IOCTL_DEF(DRM_AMD_RESETCP, radeon_ms_resetcp, DRM_AUTH),
 };
 int radeon_ms_num_ioctls = DRM_ARRAY_SIZE(radeon_ms_ioctls);
 
@@ -247,7 +247,7 @@ int radeon_ms_driver_load(struct drm_device *dev, unsigned long flags)
 	}
 
 	/* initialze driver specific */
-	ret = amd_legacy_cbuffer_initialize(dev);
+	ret = amd_legacy_cmd_module_initialize(dev);
 	if (ret != 0) {
 		radeon_ms_driver_unload(dev);
 		return ret;
@@ -286,7 +286,7 @@ int radeon_ms_driver_unload(struct drm_device *dev)
 	radeon_ms_outputs_destroy(dev);
 
 	/* shutdown specific driver */
-	amd_legacy_cbuffer_destroy(dev);
+	amd_legacy_cmd_module_destroy(dev);
 	
 	/* shutdown cp engine */
 	radeon_ms_cp_finish(dev);
diff --git a/shared-core/radeon_ms_drm.h b/shared-core/radeon_ms_drm.h
index e1b4c18c..d7fe6fab 100644
--- a/shared-core/radeon_ms_drm.h
+++ b/shared-core/radeon_ms_drm.h
@@ -27,42 +27,54 @@
  * Authors:
  *    Jérôme Glisse <glisse@freedesktop.org>
  */
-#ifndef __RADEON_MS_DRM_H__
-#define __RADEON_MS_DRM_H__
+#ifndef __AMD_DRM_H__
+#define __AMD_DRM_H__
 
 /* Fence
- * We have only one fence class as we submit command through th
- * same fifo so there is no need to synchronize buffer btw different
- * cmd stream.
  *
- * Set DRM_RADEON_FENCE_FLAG_FLUSHED if you want a flush with
+ * Set DRM_AND_FENCE_FLAG_FLUSH if you want a flush with
  * emission of the fence
  *
- * For fence type we have the native DRM EXE type and the radeon RW
- * type.
+ * For fence type we have the native DRM EXE type and the amd R & W type.
  */
-#define DRM_RADEON_FENCE_CLASS_ACCEL		0
-#define DRM_RADEON_FENCE_TYPE_RW		2
-#define DRM_RADEON_FENCE_FLAG_FLUSHED		0x01000000
+#define DRM_AMD_FENCE_CLASS_2D                  0
+#define DRM_AMD_FENCE_TYPE_R                    (1 << 1)
+#define DRM_AMD_FENCE_TYPE_W                    (1 << 2)
+#define DRM_AMD_FENCE_FLAG_FLUSH                0x01000000
 
-/* radeon ms ioctl */
-#define DRM_RADEON_EXECBUFFER			0x00
-#define DRM_RADEON_RESETCP			0x01
+/* ioctl */
+#define DRM_AMD_CMD                             0x00
+#define DRM_AMD_RESETCP                         0x01
 
-struct drm_radeon_execbuffer_arg {
-	uint64_t    next;
-	uint32_t    reloc_offset;
-	union {
-		struct drm_bo_op_req    req;
-		struct drm_bo_arg_rep   rep;
-	} d;
+/* cmd ioctl */
+
+#define DRM_AMD_CMD_BO_TYPE_INVALID             0
+#define DRM_AMD_CMD_BO_TYPE_CMD_RING            (1 << 0)
+#define DRM_AMD_CMD_BO_TYPE_CMD_INDIRECT        (1 << 1)
+#define DRM_AMD_CMD_BO_TYPE_DATA                (1 << 2)
+
+struct drm_amd_cmd_bo_offset
+{
+	uint64_t                next;
+	uint64_t                offset;
+	uint32_t		cs_id;
+};
+
+struct drm_amd_cmd_bo
+{
+	uint32_t                type;
+	uint64_t                next;
+	uint64_t                offset;
+	struct drm_bo_op_req    op_req;
+	struct drm_bo_arg_rep   op_rep;
 };
 
-struct drm_radeon_execbuffer {
-	uint32_t args_count;
-	uint64_t args;
-	uint32_t cmd_size;
-	struct drm_fence_arg fence_arg;
+struct drm_amd_cmd
+{
+	uint32_t                cdw_count;
+	uint32_t                bo_count;
+	uint64_t                bo;
+	struct drm_fence_arg    fence_arg;
 };
 
 #endif
diff --git a/shared-core/radeon_ms_exec.c b/shared-core/radeon_ms_exec.c
index 28fcc180..fc359d45 100644
--- a/shared-core/radeon_ms_exec.c
+++ b/shared-core/radeon_ms_exec.c
@@ -27,173 +27,233 @@
 #include "radeon_ms.h"
 #include "amd.h"
 
-static void radeon_ms_execbuffer_args_clean(struct drm_device *dev,
-					    struct amd_cbuffer *cbuffer,
-					    uint32_t args_count)
+static inline void amd_cmd_bo_cleanup(struct drm_device *dev,
+				      struct amd_cmd *cmd)
 {
+	struct amd_cmd_bo *bo;
+
 	mutex_lock(&dev->struct_mutex);
-	while (args_count--) {
-		drm_bo_usage_deref_locked(&cbuffer->args[args_count].buffer);
+	list_for_each_entry(bo, &cmd->bo_unused.list, list) {
+		drm_bo_usage_deref_locked(&bo->bo);
+	}
+	list_for_each_entry(bo, &cmd->bo_used.list, list) {
+		drm_bo_usage_deref_locked(&bo->bo);
 	}
 	mutex_unlock(&dev->struct_mutex);
 }
 
-static int radeon_ms_execbuffer_args(struct drm_device *dev,
-				     struct drm_file *file_priv,
-				     struct drm_radeon_execbuffer *execbuffer,
-				     struct amd_cbuffer *cbuffer)
+static inline int amd_cmd_bo_validate(struct drm_device *dev,
+				      struct drm_file *file,
+				      struct amd_cmd_bo *cmd_bo,
+				      struct drm_amd_cmd_bo *bo,
+				      uint64_t data)
+{
+	int ret;
+
+	/* validate only cmd indirect or data bo */
+	switch (bo->type) {
+	case DRM_AMD_CMD_BO_TYPE_CMD_INDIRECT:
+	case DRM_AMD_CMD_BO_TYPE_DATA:
+	case DRM_AMD_CMD_BO_TYPE_CMD_RING:
+		/* FIXME: make sure userspace can no longer map the bo */
+		break;
+	default:
+		return 0;
+	}
+	/* check that buffer operation is validate */
+	if (bo->op_req.op != drm_bo_validate) {
+		DRM_ERROR("buffer 0x%x object operation is not validate.\n",
+			  cmd_bo->handle);
+		return -EINVAL;
+	}
+	/* validate buffer */
+	memset(&bo->op_rep, 0, sizeof(struct drm_bo_arg_rep));
+	ret = drm_bo_handle_validate(file,
+				     bo->op_req.bo_req.handle,
+				     bo->op_req.bo_req.flags,
+				     bo->op_req.bo_req.mask,
+				     bo->op_req.bo_req.hint,
+				     bo->op_req.bo_req.fence_class,
+				     0,
+				     &bo->op_rep.bo_info,
+				     &cmd_bo->bo);
+	if (ret) {
+		DRM_ERROR("validate error %d for 0x%08x\n",
+			  ret, cmd_bo->handle);
+		return ret;
+	}
+	if (copy_to_user((void __user *)((unsigned)data), bo,
+			 sizeof(struct drm_amd_cmd_bo))) {
+		DRM_ERROR("failed to copy to user validate result of 0x%08x\n",
+			  cmd_bo->handle);
+		return -EFAULT;
+	}
+	return 0;
+}
+
+static int amd_cmd_parse_cmd_bo(struct drm_device *dev,
+				struct drm_file *file,
+				struct drm_amd_cmd *drm_amd_cmd,
+				struct amd_cmd *cmd)
 {
-	struct drm_radeon_execbuffer_arg arg;
-	struct drm_bo_arg_rep rep;
-	uint32_t args_count = 0;
-	uint64_t next = 0;
-	uint64_t data = execbuffer->args;
+	struct drm_amd_cmd_bo drm_amd_cmd_bo;
+	struct amd_cmd_bo *cmd_bo;
+	uint32_t bo_count = 0;
+	uint64_t data = drm_amd_cmd->bo;
 	int ret = 0;
 
 	do {
-		if (args_count >= execbuffer->args_count) {
-			DRM_ERROR("[radeon_ms] buffer count exceeded %d\n.",
-				  execbuffer->args_count);
-			ret = -EINVAL;
-			goto out_err;
+		/* check we don't have more buffer than announced */
+		if (bo_count >= drm_amd_cmd->bo_count) {
+			DRM_ERROR("cmd bo count exceeded got %d waited %d\n.",
+				  bo_count, drm_amd_cmd->bo_count);
+			return -EINVAL;
 		}
-		INIT_LIST_HEAD(&cbuffer->args[args_count].list);
-		cbuffer->args[args_count].buffer = NULL;
-		if (copy_from_user(&arg, (void __user *)((unsigned)data),
-		    sizeof(struct drm_radeon_execbuffer_arg))) {
-			ret = -EFAULT;
-			goto out_err;
+		/* initialize amd_cmd_bo */
+		cmd_bo = &cmd->bo[bo_count];
+		INIT_LIST_HEAD(&cmd_bo->list);
+		cmd_bo->bo = NULL;
+		/* copy from userspace */
+		if (copy_from_user(&drm_amd_cmd_bo,
+				   (void __user *)((unsigned)data),
+				   sizeof(struct drm_amd_cmd_bo))) {
+			return -EFAULT;
 		}
+		/* collect informations */
+		cmd_bo->type = drm_amd_cmd_bo.type;
+		cmd_bo->mask = drm_amd_cmd_bo.op_req.bo_req.mask;
+		cmd_bo->flags = drm_amd_cmd_bo.op_req.bo_req.flags;
+		cmd_bo->handle = drm_amd_cmd_bo.op_req.arg_handle;
+		/* get bo objects */
 		mutex_lock(&dev->struct_mutex);
-		cbuffer->args[args_count].buffer = 
-			drm_lookup_buffer_object(file_priv,
-						 arg.d.req.arg_handle, 1);
-		cbuffer->args[args_count].dw_id = arg.reloc_offset;
+		cmd_bo->bo = drm_lookup_buffer_object(file, cmd_bo->handle, 1);
 		mutex_unlock(&dev->struct_mutex);
-		if (arg.d.req.op != drm_bo_validate) {
-			DRM_ERROR("[radeon_ms] buffer object operation wasn't "
-				  "validate.\n");
-			ret = -EINVAL;
-			goto out_err;
+		if (cmd_bo->bo == NULL) {
+			DRM_ERROR("unknown bo handle 0x%x\n", cmd_bo->handle);
+			return -EINVAL;
 		}
-		memset(&rep, 0, sizeof(struct drm_bo_arg_rep));
-		ret = drm_bo_handle_validate(file_priv,
-					     arg.d.req.bo_req.handle,
-					     arg.d.req.bo_req.flags,
-					     arg.d.req.bo_req.mask,
-					     arg.d.req.bo_req.hint,
-					     arg.d.req.bo_req.fence_class,
-					     0,
-					     &rep.bo_info,
-					     &cbuffer->args[args_count].buffer);
+		/* validate buffer if necessary */
+		ret = amd_cmd_bo_validate(dev, file, cmd_bo,
+					  &drm_amd_cmd_bo, data);
 		if (ret) {
-			DRM_ERROR("[radeon_ms] error on handle validate %d\n",
-				  ret);
-			rep.ret = ret;
-			goto out_err;
+			mutex_lock(&dev->struct_mutex);
+			drm_bo_usage_deref_locked(&cmd_bo->bo);
+			mutex_unlock(&dev->struct_mutex);
+			return ret;
 		}
-		next = arg.next;
-		arg.d.rep = rep;
-		if (copy_to_user((void __user *)((unsigned)data), &arg,
-		    sizeof(struct drm_radeon_execbuffer_arg))) {
-			ret = -EFAULT;
-			goto out_err;
+		/* inspect bo type */
+		switch (cmd_bo->type) {
+		case DRM_AMD_CMD_BO_TYPE_CMD_INDIRECT:
+			/* add it so we properly unreference in case of error */
+			list_add_tail(&cmd_bo->list, &cmd->bo_used.list);
+			return -EINVAL;
+		case DRM_AMD_CMD_BO_TYPE_DATA:
+			/* add to unused list */
+			list_add_tail(&cmd_bo->list, &cmd->bo_unused.list);
+			break;
+		case DRM_AMD_CMD_BO_TYPE_CMD_RING:
+			/* set cdw_bo */
+			list_add_tail(&cmd_bo->list, &cmd->bo_used.list);
+			cmd->cdw_bo = cmd_bo;
+			break;
+		default:
+			mutex_lock(&dev->struct_mutex);
+			drm_bo_usage_deref_locked(&cmd_bo->bo);
+			mutex_unlock(&dev->struct_mutex);
+			DRM_ERROR("unknow bo 0x%x unknown type 0x%x in cmd\n",
+				  cmd_bo->handle, cmd_bo->type);
+			return -EINVAL;
 		}
-		data = next;
-
-		list_add_tail(&cbuffer->args[args_count].list,
-			      &cbuffer->arg_unused.list);
-
-		args_count++;
-	} while (next != 0);
-	if (args_count != execbuffer->args_count) {
-		DRM_ERROR("[radeon_ms] not enought buffer got %d waited %d\n.",
-			  args_count, execbuffer->args_count);
-		ret = -EINVAL;
-		goto out_err;
+		/* ok next bo */
+		data = drm_amd_cmd_bo.next;
+		bo_count++;
+	} while (data != 0);
+	if (bo_count != drm_amd_cmd->bo_count) {
+		DRM_ERROR("not enought buffer got %d expected %d\n.",
+			  bo_count, drm_amd_cmd->bo_count);
+		return -EINVAL;
 	}
 	return 0;
-out_err:
-	radeon_ms_execbuffer_args_clean(dev, cbuffer, args_count);
-	return ret;
 }
 
-static int cbuffer_packet0_check(struct drm_device *dev,
-				 struct amd_cbuffer *cbuffer,
-				 int dw_id)
+static int amd_cmd_packet0_check(struct drm_device *dev,
+				 struct amd_cmd *cmd,
+				 int *cdw_id)
 {
 	struct drm_radeon_private *dev_priv = dev->dev_private;
 	uint32_t reg, count, r, i;
 	int ret;
 
-	reg = cbuffer->cbuffer[dw_id] & PACKET0_REG_MASK;
-	count = (cbuffer->cbuffer[dw_id] & PACKET0_COUNT_MASK) >>
-		PACKET0_COUNT_SHIFT;
-	if (reg + count > dev_priv->cbuffer_checker.numof_p0_checkers) {
+	reg = cmd->cdw[*cdw_id] & PACKET0_REG_MASK;
+	count = (cmd->cdw[*cdw_id] & PACKET0_COUNT_MASK) >> PACKET0_COUNT_SHIFT;
+	if (reg + count > dev_priv->cmd_module.numof_p0_checkers) {
+		DRM_ERROR("0x%08X registers is above last accepted registers\n",
+			  reg << 2);
 		return -EINVAL;
 	}
 	for (r = reg, i = 0; i <= count; i++, r++) {
-		if (dev_priv->cbuffer_checker.check_p0[r] == NULL) {
+		if (dev_priv->cmd_module.check_p0[r] == NULL) {
 			continue;
 		}
-		if (dev_priv->cbuffer_checker.check_p0[r] == (void *)-1) {
-			DRM_INFO("[radeon_ms] check_f: %d %d -1 checker\n",
-			         r, r << 2);
+		if (dev_priv->cmd_module.check_p0[r] == (void *)-1) {
+			DRM_ERROR("register 0x%08X (at %d) is forbidden\n",
+			         r << 2, (*cdw_id) + i + 1);
 			return -EINVAL;
 		}
-		ret = dev_priv->cbuffer_checker.check_p0[r](dev, cbuffer,
-							    dw_id + i + 1, reg);
+		ret = dev_priv->cmd_module.check_p0[r](dev, cmd,
+						       (*cdw_id) + i + 1, r);
 		if (ret) {
-			DRM_INFO("[radeon_ms] check_f: %d %d checker ret=%d\n",
-			         r, r << 2, ret);
-			return -EINVAL;
+			return ret;
 		}
 	}
 	/* header + N + 1 dword passed test */
-	return count + 2;
+	(*cdw_id) += count + 2;
+	return 0;
 }
 
-static int cbuffer_packet3_check(struct drm_device *dev,
-				 struct amd_cbuffer *cbuffer,
-				 int dw_id)
+static int amd_cmd_packet3_check(struct drm_device *dev,
+				 struct amd_cmd *cmd,
+				 int *cdw_id)
 {
 	struct drm_radeon_private *dev_priv = dev->dev_private;
 	uint32_t opcode, count;
 	int ret;
 
-	opcode = (cbuffer->cbuffer[dw_id] & PACKET3_OPCODE_MASK) >>
+	opcode = (cmd->cdw[*cdw_id] & PACKET3_OPCODE_MASK) >>
 		 PACKET3_OPCODE_SHIFT;
-	if (opcode > dev_priv->cbuffer_checker.numof_p3_checkers) {
+	if (opcode > dev_priv->cmd_module.numof_p3_checkers) {
+		DRM_ERROR("0x%08X opcode is above last accepted opcodes\n",
+			  opcode);
 		return -EINVAL;
 	}
-	count = (cbuffer->cbuffer[dw_id] & PACKET3_COUNT_MASK) >>
-		PACKET3_COUNT_SHIFT;
-	if (dev_priv->cbuffer_checker.check_p3[opcode] == NULL) {
+	count = (cmd->cdw[*cdw_id] & PACKET3_COUNT_MASK) >> PACKET3_COUNT_SHIFT;
+	if (dev_priv->cmd_module.check_p3[opcode] == NULL) {
+		DRM_ERROR("0x%08X opcode is forbidden\n", opcode);
 		return -EINVAL;
 	}
-	ret = dev_priv->cbuffer_checker.check_p3[opcode](dev, cbuffer,
-							 dw_id + 1, opcode,
-							 count);
+	ret = dev_priv->cmd_module.check_p3[opcode](dev, cmd,
+						    (*cdw_id) + 1, opcode,
+						    count);
 	if (ret) {
-		return -EINVAL;
+		return ret;
 	}
-	return count + 2;
+	/* header + N + 1 dword passed test */
+	(*cdw_id) += count + 2;
+	return 0;
 }
 
-int amd_cbuffer_check(struct drm_device *dev, struct amd_cbuffer *cbuffer)
+int amd_cmd_check(struct drm_device *dev, struct amd_cmd *cmd)
 {
 	uint32_t i;
 	int ret;
 
-	for (i = 0; i < cbuffer->cbuffer_dw_count;) {
-		switch (PACKET_HEADER_GET(cbuffer->cbuffer[i])) {
+	for (i = 0; i < cmd->cdw_count;) {
+		switch (PACKET_HEADER_GET(cmd->cdw[i])) {
 		case 0:
-			ret = cbuffer_packet0_check(dev, cbuffer, i);
-			if (ret <= 0) {
+			ret = amd_cmd_packet0_check(dev, cmd, &i);
+			if (ret) {
 				return ret;
 			}
-			/* advance to next packet */
-			i += ret;
 			break;
 		case 1:
 			/* we don't accept packet 1 */
@@ -202,122 +262,122 @@ int amd_cbuffer_check(struct drm_device *dev, struct amd_cbuffer *cbuffer)
 			/* FIXME: accept packet 2 */
 			return -EINVAL;
 		case 3:
-			ret = cbuffer_packet3_check(dev, cbuffer, i);
-			if (ret <= 0) {
+			ret = amd_cmd_packet3_check(dev, cmd, &i);
+			if (ret) {
 				return ret;
 			}
-			/* advance to next packet */
-			i += ret;
 			break;
 		}
 	}
 	return 0;
 }
 
-struct amd_cbuffer_arg *
-amd_cbuffer_arg_from_dw_id(struct amd_cbuffer_arg *head, uint32_t dw_id)
+static int amd_ioctl_cmd_cleanup(struct drm_device *dev,
+				 struct drm_file *file,
+				 struct amd_cmd *cmd,
+				 int r)
 {
-	struct amd_cbuffer_arg *arg;
-
-	list_for_each_entry(arg, &head->list, list) {
-		if (arg->dw_id == dw_id) {
-			return arg;
-		}
+	/* check if we need to unfence object */
+	if (r && (!list_empty(&cmd->bo_unused.list) ||
+		  !list_empty(&cmd->bo_unused.list))) {
+		drm_putback_buffer_objects(dev);		
+	}
+	if (cmd->cdw) {
+		drm_bo_kunmap(&cmd->cdw_kmap);
+		cmd->cdw = NULL;
 	}
-	/* no buffer at this dw index */
-	return NULL;
+	/* derefence buffer as lookup reference them */
+	amd_cmd_bo_cleanup(dev, cmd);
+	if (cmd->bo) {
+		drm_free(cmd->bo,
+			 cmd->bo_count * sizeof(struct amd_cmd_bo),
+		 	 DRM_MEM_DRIVER);
+		cmd->bo = NULL;
+	}
+	drm_bo_read_unlock(&dev->bm.bm_lock);
+	return r;
 }
 
-
-int radeon_ms_execbuffer(struct drm_device *dev, void *data,
-			 struct drm_file *file_priv)
+int amd_ioctl_cmd(struct drm_device *dev, void *data, struct drm_file *file)
 {
 	struct drm_radeon_private *dev_priv = dev->dev_private;
-	struct drm_radeon_execbuffer *execbuffer = data;
-	struct drm_fence_arg *fence_arg = &execbuffer->fence_arg;
-	struct drm_bo_kmap_obj cmd_kmap;
+	struct drm_amd_cmd *drm_amd_cmd = data;
+	struct drm_fence_arg *fence_arg = &drm_amd_cmd->fence_arg;
 	struct drm_fence_object *fence;
-	int cmd_is_iomem;
-	int ret = 0;
-	struct amd_cbuffer cbuffer;
+	struct amd_cmd cmd;
+	int tmp;
+	int ret;
 
-	/* command buffer dword count must be >= 0 */
-	if (execbuffer->cmd_size < 0) {
+	/* check that we have a command checker */
+	if (dev_priv->cmd_module.check == NULL) {
+		DRM_ERROR("invalid command checker module.\n");
+		return -EFAULT;
+	}
+	/* command dword count must be >= 0 */
+	if (drm_amd_cmd->cdw_count == 0) {
+		DRM_ERROR("command dword count is 0.\n");
 		return -EINVAL;
 	}
-
-	/* FIXME: Lock buffer manager, is this really needed ?
-	 */
+	/* FIXME: Lock buffer manager, is this really needed ? */
 	ret = drm_bo_read_lock(&dev->bm.bm_lock);
 	if (ret) {
+		DRM_ERROR("bo read locking failed.\n");
 		return ret;
 	}
-
-	cbuffer.args = drm_calloc(execbuffer->args_count,
-				  sizeof(struct amd_cbuffer_arg),
-				  DRM_MEM_DRIVER);
-	if (cbuffer.args == NULL) {
-		ret = -ENOMEM;
-		goto out_free;
+	/* cleanup & initialize amd cmd structure */
+	memset(&cmd, 0, sizeof(struct amd_cmd));
+	cmd.bo_count = drm_amd_cmd->bo_count;
+	INIT_LIST_HEAD(&cmd.bo_unused.list);
+	INIT_LIST_HEAD(&cmd.bo_used.list);
+	/* allocate structure for bo parsing */
+	cmd.bo = drm_calloc(cmd.bo_count, sizeof(struct amd_cmd_bo),
+			    DRM_MEM_DRIVER);
+	if (cmd.bo == NULL) {
+		return amd_ioctl_cmd_cleanup(dev, file, &cmd, -ENOMEM);
         }
-
-	INIT_LIST_HEAD(&cbuffer.arg_unused.list);
-	INIT_LIST_HEAD(&cbuffer.arg_used.list);
-
-	/* process arguments */
-	ret = radeon_ms_execbuffer_args(dev, file_priv, execbuffer, &cbuffer);
+	/* parse cmd bo */
+	ret = amd_cmd_parse_cmd_bo(dev, file, drm_amd_cmd, &cmd);
 	if (ret) {
-		DRM_ERROR("[radeon_ms] execbuffer wrong arguments\n");
-		goto out_free;
+		return amd_ioctl_cmd_cleanup(dev, file, &cmd, ret);
+	}
+	/* check that a command buffer have been found */
+	if (cmd.cdw_bo == NULL) {
+		DRM_ERROR("no command buffer submited in cmd ioctl\n");
+		return amd_ioctl_cmd_cleanup(dev, file, &cmd, -EINVAL);
 	}
-
 	/* map command buffer */
-	cbuffer.cbuffer_dw_count = (cbuffer.args[0].buffer->mem.num_pages *
-				    PAGE_SIZE) >> 2;
-	if (execbuffer->cmd_size > cbuffer.cbuffer_dw_count) {
-		ret = -EINVAL;
-		goto out_free_release;
+	cmd.cdw_count = drm_amd_cmd->cdw_count;
+	cmd.cdw_size = (cmd.cdw_bo->bo->mem.num_pages * PAGE_SIZE) >> 2;
+	if (cmd.cdw_size < cmd.cdw_count) {
+		DRM_ERROR("command buffer (%d) is smaller than expected (%d)\n",
+			  cmd.cdw_size, cmd.cdw_count);
+		return amd_ioctl_cmd_cleanup(dev, file, &cmd, -EINVAL);
 	}
-	cbuffer.cbuffer_dw_count = execbuffer->cmd_size;
-	memset(&cmd_kmap, 0, sizeof(struct drm_bo_kmap_obj));
-	ret = drm_bo_kmap(cbuffer.args[0].buffer, 0,
-		          cbuffer.args[0].buffer->mem.num_pages, &cmd_kmap);
+	memset(&cmd.cdw_kmap, 0, sizeof(struct drm_bo_kmap_obj));
+	ret = drm_bo_kmap(cmd.cdw_bo->bo, 0,
+			  cmd.cdw_bo->bo->mem.num_pages, &cmd.cdw_kmap);
 	if (ret) {
-		DRM_ERROR("[radeon_ms] error mapping ring buffer: %d\n", ret);
-		goto out_free_release;
+		DRM_ERROR("error mapping command buffer\n");
+		return amd_ioctl_cmd_cleanup(dev, file, &cmd, ret);
 	}
-	cbuffer.cbuffer = drm_bmo_virtual(&cmd_kmap, &cmd_is_iomem);
-	list_del(&cbuffer.args[0].list);
-	list_add_tail(&cbuffer.args[0].list , &cbuffer.arg_used.list);
-
-	/* do cmd checking & relocations */
-	if (dev_priv->cbuffer_checker.check) {
-		ret = dev_priv->cbuffer_checker.check(dev, &cbuffer);
-		if (ret) {
-			drm_putback_buffer_objects(dev);
-			goto out_free_release;
-		}
-	} else {
-		drm_putback_buffer_objects(dev);
-		goto out_free_release;
+	cmd.cdw = drm_bmo_virtual(&cmd.cdw_kmap, &tmp);
+	/* do command checking */
+	ret = dev_priv->cmd_module.check(dev, &cmd);
+	if (ret) {
+		return amd_ioctl_cmd_cleanup(dev, file, &cmd, ret);
 	}
-
-	ret = radeon_ms_ring_emit(dev, cbuffer.cbuffer,
-				  cbuffer.cbuffer_dw_count);
+	/* copy command to ring */
+	ret = radeon_ms_ring_emit(dev, cmd.cdw, cmd.cdw_count);
 	if (ret) {
-		drm_putback_buffer_objects(dev);
-		goto out_free_release;
+		return amd_ioctl_cmd_cleanup(dev, file, &cmd, ret);
 	}
-
 	/* fence */
 	ret = drm_fence_buffer_objects(dev, NULL, 0, NULL, &fence);
 	if (ret) {
-		drm_putback_buffer_objects(dev);
-		DRM_ERROR("[radeon_ms] fence buffer objects failed\n");
-		goto out_free_release;
+		return amd_ioctl_cmd_cleanup(dev, file, &cmd, ret);
 	}
 	if (!(fence_arg->flags & DRM_FENCE_FLAG_NO_USER)) {
-		ret = drm_fence_add_user_object(file_priv, fence,
+		ret = drm_fence_add_user_object(file, fence,
 						fence_arg->flags &
 						DRM_FENCE_FLAG_SHAREABLE);
 		if (!ret) {
@@ -326,16 +386,10 @@ int radeon_ms_execbuffer(struct drm_device *dev, void *data,
 			fence_arg->type = fence->type;
 			fence_arg->signaled = fence->signaled_types;
 			fence_arg->sequence = fence->sequence;
+		} else {
+			DRM_ERROR("error add object fence, expect oddity !\n");
 		}
 	}
 	drm_fence_usage_deref_unlocked(&fence);
-out_free_release:
-	drm_bo_kunmap(&cmd_kmap);
-	radeon_ms_execbuffer_args_clean(dev, &cbuffer, execbuffer->args_count);
-out_free:
-	drm_free(cbuffer.args,
-		 (execbuffer->args_count * sizeof(struct amd_cbuffer_arg)),
-		 DRM_MEM_DRIVER);
-	drm_bo_read_unlock(&dev->bm.bm_lock);
-	return ret;
+	return amd_ioctl_cmd_cleanup(dev, file, &cmd, 0);
 }
diff --git a/shared-core/radeon_ms_fence.c b/shared-core/radeon_ms_fence.c
index 994c3e48..08e53bd2 100644
--- a/shared-core/radeon_ms_fence.c
+++ b/shared-core/radeon_ms_fence.c
@@ -44,7 +44,10 @@ static inline int r3xx_fence_emit_sequence(struct drm_device *dev,
 			sequence & ~R3XX_FENCE_SEQUENCE_RW_FLUSH;
 		/* Ask flush for VERTEX & FRAGPROG pipeline
 		 * have 3D idle  */
+		/* FIXME: proper flush */
+#if 0
 		dev_priv->flush_cache(dev);
+#endif
 	}
 	cmd[0] = CP_PACKET0(dev_priv->fence_reg, 0);
 	cmd[1] = sequence;
@@ -78,18 +81,17 @@ static inline void r3xx_fence_report(struct drm_device *dev,
 		return;
 	}
 	sequence = mmio_read(dev_priv, dev_priv->fence_reg);
+DRM_INFO("%s pass fence 0x%08x\n", __func__, sequence);
 	if (sequence & R3XX_FENCE_SEQUENCE_RW_FLUSH) {
 		sequence &= ~R3XX_FENCE_SEQUENCE_RW_FLUSH;
-		fence_types |= DRM_RADEON_FENCE_TYPE_RW;
+		fence_types |= DRM_AMD_FENCE_TYPE_R;
+		fence_types |= DRM_AMD_FENCE_TYPE_W;
 		if (sequence == r3xx_fence->sequence_last_flush) {
 			r3xx_fence->sequence_last_flush = 0;
 		}
 	}
-	/* avoid to report already reported sequence */
-	if (sequence != r3xx_fence->sequence_last_reported) {
-		drm_fence_handler(dev, 0, sequence, fence_types, 0);
-		r3xx_fence->sequence_last_reported = sequence;
-	}
+	drm_fence_handler(dev, 0, sequence, fence_types, 0);
+	r3xx_fence->sequence_last_reported = sequence;
 }
 
 static void r3xx_fence_flush(struct drm_device *dev, uint32_t class)
@@ -116,9 +118,10 @@ static void r3xx_fence_poll(struct drm_device *dev, uint32_t fence_class,
 	}
 	/* if there is a RW flush pending then submit new sequence
 	 * preceded by flush cmds */
-	if (fc->pending_flush & DRM_RADEON_FENCE_TYPE_RW) {
+	if (fc->pending_flush & (DRM_AMD_FENCE_TYPE_R | DRM_AMD_FENCE_TYPE_W)) {
 		r3xx_fence_flush(dev, 0);
-		fc->pending_flush &= ~DRM_RADEON_FENCE_TYPE_RW;
+		fc->pending_flush &= ~DRM_AMD_FENCE_TYPE_R;
+		fc->pending_flush &= ~DRM_AMD_FENCE_TYPE_W;
 	}
 	r3xx_fence_report(dev, dev_priv, r3xx_fence);
 	return;
@@ -137,10 +140,12 @@ static int r3xx_fence_emit(struct drm_device *dev, uint32_t class,
 	}
 	*sequence = tmp = r3xx_fence_sequence(r3xx_fence);
 	*native_type = DRM_FENCE_TYPE_EXE;
-	if (flags & DRM_RADEON_FENCE_FLAG_FLUSHED) {
-		*native_type |= DRM_RADEON_FENCE_TYPE_RW;
+	if (flags & DRM_AMD_FENCE_FLAG_FLUSH) {
+		*native_type |= DRM_AMD_FENCE_TYPE_R;
+		*native_type |= DRM_AMD_FENCE_TYPE_W;
 		tmp |= R3XX_FENCE_SEQUENCE_RW_FLUSH;
 	}
+DRM_INFO("%s emit fence 0x%08x\n", __func__, tmp);
 	return r3xx_fence_emit_sequence(dev, dev_priv, tmp);
 }
 
@@ -148,7 +153,8 @@ static int r3xx_fence_has_irq(struct drm_device *dev,
 			      uint32_t class, uint32_t type)
 {
 	const uint32_t type_irq_mask = DRM_FENCE_TYPE_EXE |
-				       DRM_RADEON_FENCE_TYPE_RW;
+				       DRM_AMD_FENCE_TYPE_R |
+				       DRM_AMD_FENCE_TYPE_W;
 	/*
 	 * We have an irq for EXE & RW fence.
 	 */
@@ -243,7 +249,9 @@ int r3xx_fence_types(struct drm_buffer_object *bo,
 {
 	*class = 0;
 	if (bo->mem.flags & (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE)) {
-		*type = DRM_FENCE_TYPE_EXE | DRM_RADEON_FENCE_TYPE_RW;
+		*type = DRM_FENCE_TYPE_EXE |
+			DRM_AMD_FENCE_TYPE_R |
+			DRM_AMD_FENCE_TYPE_W;
 	} else {
 		*type = DRM_FENCE_TYPE_EXE;
 	}