diff options
| author | Jerome Glisse <glisse@freedesktop.org> | 2008-01-15 14:05:25 +0100 |
|---|---|---|
| committer | John Doe <glisse@freedesktop.org> | 2008-01-15 14:17:05 +0100 |
| commit | f1f934c8c97d6664fb5e1920a41154c09cc7f293 (patch) | |
| tree | bfa707e2d430643b4f5ab7a94a7f59508ae60127 /shared-core/radeon_ms_reg.h | |
| parent | e6fc47129ffe972bbee1c08fd822a8c171f21322 (diff) | |
radeon_ms: add rom parsing & adapt code
Add rom (only combios for now) parsing and use informations
retrieve instead of hardcoded table. Shuffle code around a
bit.
Diffstat (limited to 'shared-core/radeon_ms_reg.h')
| -rw-r--r-- | shared-core/radeon_ms_reg.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/shared-core/radeon_ms_reg.h b/shared-core/radeon_ms_reg.h index d450280c..56963c63 100644 --- a/shared-core/radeon_ms_reg.h +++ b/shared-core/radeon_ms_reg.h @@ -827,6 +827,32 @@ #define GPIO_DDC2__SW_CAN_USE_DVI_I2C 0x00100000 #define GPIO_DDC2__SW_DONE_USING_DVI_I2C 0x00200000 #define GPIO_DDC2__HW_USING_DVI_I2C 0x00400000 +#define GPIO_DVI_DDC 0x00000064 +#define GPIO_DVI_DDC__DVI_DDC_DATA_OUTPUT 0x00000001 +#define GPIO_DVI_DDC__DVI_DCC_DATA_OUTPUT 0x00000001 +#define GPIO_DVI_DDC__DVI_DDC_CLK_OUTPUT 0x00000002 +#define GPIO_DVI_DDC__DVI_DDC_DATA_INPUT 0x00000100 +#define GPIO_DVI_DDC__DVI_DDC_CLK_INPUT 0x00000200 +#define GPIO_DVI_DDC__DVI_DDC_DATA_OUT_EN 0x00010000 +#define GPIO_DVI_DDC__DVI_DDC_CLK_OUT_EN 0x00020000 +#define GPIO_DVI_DDC__SW_WANTS_TO_USE_DVI_I2C 0x00100000 +#define GPIO_DVI_DDC__SW_CAN_USE_DVI_I2C 0x00100000 +#define GPIO_DVI_DDC__SW_DONE_USING_DVI_I2C 0x00200000 +#define GPIO_DVI_DDC__HW_USING_DVI_I2C 0x00400000 +#define GPIO_MONID 0x00000068 +#define GPIO_MONID__GPIO_MONID_0_OUTPUT 0x00000001 +#define GPIO_MONID__GPIO_MONID_1_OUTPUT 0x00000002 +#define GPIO_MONID__GPIO_MONID_0_INPUT 0x00000100 +#define GPIO_MONID__GPIO_MONID_1_INPUT 0x00000200 +#define GPIO_MONID__GPIO_MONID_0_OUT_EN 0x00010000 +#define GPIO_MONID__GPIO_MONID_1_OUT_EN 0x00020000 +#define GPIO_CRT2_DDC 0x0000006C +#define GPIO_CRT2_DDC__CRT2_DDC_DATA_OUTPUT 0x00000001 +#define GPIO_CRT2_DDC__CRT2_DDC_CLK_OUTPUT 0x00000002 +#define GPIO_CRT2_DDC__CRT2_DDC_DATA_INPUT 0x00000100 +#define GPIO_CRT2_DDC__CRT2_DDC_CLK_INPUT 0x00000200 +#define GPIO_CRT2_DDC__CRT2_DDC_DATA_OUT_EN 0x00010000 +#define GPIO_CRT2_DDC__CRT2_DDC_CLK_OUT_EN 0x00020000 #define CLOCK_CNTL_INDEX 0x00000008 #define CLOCK_CNTL_INDEX__PLL_ADDR__MASK 0x0000001F #define CLOCK_CNTL_INDEX__PLL_ADDR__SHIFT 0 |