diff options
| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2008-11-13 15:30:06 -0800 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2008-11-13 15:30:06 -0800 |
| commit | 965b4d662a5236ee5aeb94a70f62565b6ed5644c (patch) | |
| tree | 7645e5130046e3952c2a490d5561bafe67cbff89 /shared-core/radeon_drv.h | |
| parent | 9a4cb7eab4f74747cc777a3fef31dbb46e1191e5 (diff) | |
| parent | 7e27b3ba88f0c40680380636a436c18e3220c7ce (diff) | |
Merge branch 'master' into modesetting-gem
Conflicts:
libdrm/Makefile.am
libdrm/intel/intel_bufmgr.h
libdrm/intel/intel_bufmgr_fake.c
libdrm/intel/intel_bufmgr_gem.c
shared-core/drm.h
shared-core/i915_dma.c
shared-core/i915_irq.c
shared-core/radeon_cp.c
shared-core/radeon_drv.h
Diffstat (limited to 'shared-core/radeon_drv.h')
| -rw-r--r-- | shared-core/radeon_drv.h | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index cf3084e1..50f0b171 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -598,12 +598,31 @@ int radeon_resume(struct drm_device *dev); # define RADEON_SCISSOR_1_ENABLE (1 << 29) # define RADEON_SCISSOR_2_ENABLE (1 << 30) +/* + * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx) + * don't have an explicit bus mastering disable bit. It's handled + * by the PCI D-states. PMI_BM_DIS disables D-state bus master + * handling, not bus mastering itself. + */ #define RADEON_BUS_CNTL 0x0030 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ # define RADEON_BUS_MASTER_DIS (1 << 6) /* rs600/rs690/rs740 */ # define RS600_BUS_MASTER_DIS (1 << 14) # define RS600_MSI_REARM (1 << 20) +/* see RS480_MSI_REARM in AIC_CNTL for rs480 */ + +#define RADEON_BUS_CNTL1 0x0034 +# define RADEON_PMI_BM_DIS (1 << 2) +# define RADEON_PMI_INT_DIS (1 << 3) + +#define RV370_BUS_CNTL 0x004c +# define RV370_PMI_BM_DIS (1 << 5) +# define RV370_PMI_INT_DIS (1 << 6) + +#define RADEON_MSI_REARM_EN 0x0160 +/* rv370/rv380, rv410, r423/r430/r480, r5xx */ +# define RV370_MSI_REARM_EN (1 << 0) #define RADEON_CLOCK_CNTL_DATA 0x000c # define RADEON_PLL_WR_EN (1 << 7) @@ -1385,10 +1404,11 @@ do { \ #define IGP_WRITE_MCIND(addr, val) \ do { \ - if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \ - RS690_WRITE_MCIND(addr, val); \ - else \ - RS480_WRITE_MCIND(addr, val); \ + if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \ + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \ + RS690_WRITE_MCIND( addr, val ); \ + else \ + RS480_WRITE_MCIND( addr, val ); \ } while (0) #define CP_PACKET0( reg, n ) \ |