diff options
| author | Dave Airlie <airlied@linux.ie> | 2004-08-17 11:24:50 +0000 |
|---|---|---|
| committer | Dave Airlie <airlied@linux.ie> | 2004-08-17 11:24:50 +0000 |
| commit | 93e8c201afac565942f9d3523ac808d3220d6d0e (patch) | |
| tree | c11a441ca4741c51d1de5c90414bdbce5eeb1997 /shared-core/radeon_drv.h | |
| parent | 02ef96053ccbe4c20827ec8006455906e7fb2360 (diff) | |
preparation patch for radeon permanent mapping registers/framebuffer makes
dev_priv live always, and add AGP detection in kernel patch:
radeon-pre-2.patch From: Jon Smirl
Diffstat (limited to 'shared-core/radeon_drv.h')
| -rw-r--r-- | shared-core/radeon_drv.h | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 81b9a98e..eb2d4dca 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -40,6 +40,7 @@ enum radeon_chip_flags { CHIP_IS_MOBILITY = 0x00010000UL, CHIP_IS_IGP = 0x00020000UL, CHIP_SINGLE_CRTC = 0x00040000UL, + CHIP_IS_AGP = 0x00080000UL, }; #define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 ) @@ -81,6 +82,9 @@ struct mem_block { }; typedef struct drm_radeon_private { + + u32 flags; /* see radeon_chip_flags */ + drm_radeon_ring_buffer_t ring; drm_radeon_sarea_t *sarea_priv; @@ -103,7 +107,6 @@ typedef struct drm_radeon_private { int is_r200; - int is_pci; unsigned long phys_pci_gart; dma_addr_t bus_pci_gart; @@ -223,13 +226,13 @@ extern void radeon_do_release(drm_device_t *dev); #define RADEON_BOX_WAIT_IDLE 0x8 #define RADEON_BOX_TEXTURE_LOAD 0x10 - - /* Register definitions, register access macros and drmAddMap constants * for Radeon kernel driver. */ - #define RADEON_AGP_COMMAND 0x0f60 +#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ +# define RADEON_AGP_ENABLE (1<<8) + #define RADEON_AUX_SCISSOR_CNTL 0x26f0 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) @@ -252,6 +255,11 @@ extern void radeon_do_release(drm_device_t *dev); #define RADEON_CRTC2_OFFSET 0x0324 #define RADEON_CRTC2_OFFSET_CNTL 0x0328 +#define RADEON_MPP_TB_CONFIG 0x01c0 +#define RADEON_MEM_CNTL 0x0140 +#define RADEON_MEM_SDRAM_MODE_REG 0x0158 +#define RADEON_AGP_BASE 0x0170 + #define RADEON_RB3D_COLOROFFSET 0x1c40 #define RADEON_RB3D_COLORPITCH 0x1c48 @@ -730,7 +738,9 @@ do { \ } while (0) extern int RADEON_READ_PLL( drm_device_t *dev, int addr ); - +extern int radeon_preinit( drm_device_t *dev, unsigned long flags ); +extern int radeon_postinit( drm_device_t *dev, unsigned long flags ); +extern void radeon_postcleanup( drm_device_t *dev ); #define CP_PACKET0( reg, n ) \ (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) |