diff options
| author | Michel Dänzer <michel@tungstengraphics.com> | 2006-09-15 16:37:47 +0200 |
|---|---|---|
| committer | Michel Dänzer <michel@tungstengraphics.com> | 2006-09-15 16:55:40 +0200 |
| commit | 6ba9127753eff7615ba553fbc567aec98ecf8104 (patch) | |
| tree | 4f6bd9a8e2cc6ea7155fc1b7742aceb2081dc337 /shared-core/radeon_drv.h | |
| parent | 3cc64a943a7240c73c92ab103ba0502b9ec07fee (diff) | |
Use register writes instead of BITBLT_MULTI packets for buffer swap blits.
This takes up two more ring buffer entries per rectangle blitted but makes sure
the blit is performed top to bottom, reducing the likelyhood of tearing.
Diffstat (limited to 'shared-core/radeon_drv.h')
| -rw-r--r-- | shared-core/radeon_drv.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 5fc93310..6ea2a175 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -423,6 +423,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp, #define RADEON_RB3D_COLOROFFSET 0x1c40 #define RADEON_RB3D_COLORPITCH 0x1c48 +#define RADEON_SRC_X_Y 0x1590 + #define RADEON_DP_GUI_MASTER_CNTL 0x146c # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) @@ -440,6 +442,7 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp, # define RADEON_ROP3_S 0x00cc0000 # define RADEON_ROP3_P 0x00f00000 #define RADEON_DP_WRITE_MASK 0x16cc +#define RADEON_SRC_PITCH_OFFSET 0x1428 #define RADEON_DST_PITCH_OFFSET 0x142c #define RADEON_DST_PITCH_OFFSET_C 0x1c80 # define RADEON_DST_TILE_LINEAR (0 << 30) |