diff options
| author | Jerome Glisse <glisse@freedesktop.org> | 2008-06-13 09:54:05 +0200 |
|---|---|---|
| committer | Jerome Glisse <glisse@freedesktop.org> | 2008-06-13 09:54:05 +0200 |
| commit | 1aafbb83d97ccc78b78d5cbd311f1239a3dad11e (patch) | |
| tree | c06b6f8e000dadd43be01d718c36ab2116a59644 /shared-core/r300_reg.h | |
| parent | 5d99e79c3ee027a035d4ef0a920e3fc30bd053c1 (diff) | |
radeon: r345xx fixe hard lockup
This patch should fixe hard lockup and convert them in
softlockup (ie you can ssh the box but the gpu is busted
and we are waiting in loop for it to come back to reason).
Diffstat (limited to 'shared-core/r300_reg.h')
| -rw-r--r-- | shared-core/r300_reg.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/shared-core/r300_reg.h b/shared-core/r300_reg.h index 1920ab07..d35dd39d 100644 --- a/shared-core/r300_reg.h +++ b/shared-core/r300_reg.h @@ -320,7 +320,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and * avoids bugs caused by still running shaders reading bad data from memory. */ -#define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */ +#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 /* Absolutely no clue what this register is about. */ #define R300_VAP_UNKNOWN_2288 0x2288 @@ -516,7 +516,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* gap */ /* Zero to flush caches. */ -#define R300_TX_CNTL 0x4100 +#define R300_TX_INVALTAGS 0x4100 #define R300_TX_FLUSH 0x0 /* The upper enable bits are guessed, based on fglrx reported limits. */ @@ -1365,6 +1365,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ #define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ +#define R300_RB3D_AARESOLVE_CTL 0x4E88 /* gap */ /* Guess by Vladimir. |