summaryrefslogtreecommitdiff
path: root/shared-core/r128_state.c
diff options
context:
space:
mode:
authorMichel Daenzer <michel@daenzer.net>2003-10-16 14:18:52 +0000
committerMichel Daenzer <michel@daenzer.net>2003-10-16 14:18:52 +0000
commit355b204de0dbc01308bebc77c4c1c0a9a402cded (patch)
tree92991f75592e00d3bf4af5c8ce92ac60340ca788 /shared-core/r128_state.c
parenta64dab132375b4bf5d4e8aeecc1bf341879482fa (diff)
Introduce COMMIT_RING() as in radeon DRM, stop using error prone writeback
for ring read pointer (Paul Mackerras) Get rid of some superfluous stuff, minor fixes
Diffstat (limited to 'shared-core/r128_state.c')
-rw-r--r--shared-core/r128_state.c32
1 files changed, 24 insertions, 8 deletions
diff --git a/shared-core/r128_state.c b/shared-core/r128_state.c
index 5416d35e..f411657f 100644
--- a/shared-core/r128_state.c
+++ b/shared-core/r128_state.c
@@ -45,7 +45,7 @@ static void r128_emit_clip_rects( drm_r128_private_t *dev_priv,
RING_LOCALS;
DRM_DEBUG( " %s\n", __FUNCTION__ );
- BEGIN_RING( 17 );
+ BEGIN_RING( (count < 3? count: 3) * 5 + 2 );
if ( count >= 1 ) {
OUT_RING( CCE_PACKET0( R128_AUX1_SC_LEFT, 3 ) );
@@ -1269,6 +1269,7 @@ int r128_cce_clear( DRM_IOCTL_ARGS )
sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
r128_cce_dispatch_clear( dev, &clear );
+ COMMIT_RING();
/* Make sure we restore the 3D state next time.
*/
@@ -1304,8 +1305,10 @@ int r128_do_cleanup_pageflip( drm_device_t *dev )
R128_WRITE( R128_CRTC_OFFSET, dev_priv->crtc_offset );
R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl );
- if (dev_priv->current_page != 0)
+ if (dev_priv->current_page != 0) {
r128_cce_dispatch_flip( dev );
+ COMMIT_RING();
+ }
dev_priv->page_flipping = 0;
return 0;
@@ -1330,6 +1333,7 @@ int r128_cce_flip( DRM_IOCTL_ARGS )
r128_cce_dispatch_flip( dev );
+ COMMIT_RING();
return 0;
}
@@ -1351,6 +1355,7 @@ int r128_cce_swap( DRM_IOCTL_ARGS )
dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT |
R128_UPLOAD_MASKS);
+ COMMIT_RING();
return 0;
}
@@ -1410,6 +1415,7 @@ int r128_cce_vertex( DRM_IOCTL_ARGS )
r128_cce_dispatch_vertex( dev, buf );
+ COMMIT_RING();
return 0;
}
@@ -1481,6 +1487,7 @@ int r128_cce_indices( DRM_IOCTL_ARGS )
r128_cce_dispatch_indices( dev, buf, elts.start, elts.end, count );
+ COMMIT_RING();
return 0;
}
@@ -1490,6 +1497,7 @@ int r128_cce_blit( DRM_IOCTL_ARGS )
drm_device_dma_t *dma = dev->dma;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_blit_t blit;
+ int ret;
LOCK_TEST_WITH_RETURN( dev, filp );
@@ -1507,7 +1515,10 @@ int r128_cce_blit( DRM_IOCTL_ARGS )
RING_SPACE_TEST_WITH_RETURN( dev_priv );
VB_AGE_TEST_WITH_RETURN( dev_priv );
- return r128_cce_dispatch_blit( filp, dev, &blit );
+ ret = r128_cce_dispatch_blit( filp, dev, &blit );
+
+ COMMIT_RING();
+ return ret;
}
int r128_cce_depth( DRM_IOCTL_ARGS )
@@ -1515,6 +1526,7 @@ int r128_cce_depth( DRM_IOCTL_ARGS )
DRM_DEVICE;
drm_r128_private_t *dev_priv = dev->dev_private;
drm_r128_depth_t depth;
+ int ret;
LOCK_TEST_WITH_RETURN( dev, filp );
@@ -1523,18 +1535,20 @@ int r128_cce_depth( DRM_IOCTL_ARGS )
RING_SPACE_TEST_WITH_RETURN( dev_priv );
+ ret = DRM_ERR(EINVAL);
switch ( depth.func ) {
case R128_WRITE_SPAN:
- return r128_cce_dispatch_write_span( dev, &depth );
+ ret = r128_cce_dispatch_write_span( dev, &depth );
case R128_WRITE_PIXELS:
- return r128_cce_dispatch_write_pixels( dev, &depth );
+ ret = r128_cce_dispatch_write_pixels( dev, &depth );
case R128_READ_SPAN:
- return r128_cce_dispatch_read_span( dev, &depth );
+ ret = r128_cce_dispatch_read_span( dev, &depth );
case R128_READ_PIXELS:
- return r128_cce_dispatch_read_pixels( dev, &depth );
+ ret = r128_cce_dispatch_read_pixels( dev, &depth );
}
- return DRM_ERR(EINVAL);
+ COMMIT_RING();
+ return ret;
}
int r128_cce_stipple( DRM_IOCTL_ARGS )
@@ -1557,6 +1571,7 @@ int r128_cce_stipple( DRM_IOCTL_ARGS )
r128_cce_dispatch_stipple( dev, mask );
+ COMMIT_RING();
return 0;
}
@@ -1632,6 +1647,7 @@ int r128_cce_indirect( DRM_IOCTL_ARGS )
*/
r128_cce_dispatch_indirect( dev, buf, indirect.start, indirect.end );
+ COMMIT_RING();
return 0;
}