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authorEric Anholt <eric@anholt.net>2007-09-19 15:55:58 -0700
committerEric Anholt <eric@anholt.net>2007-09-19 15:55:58 -0700
commit3d3a96ad4e5596187236898ca241515a21661b69 (patch)
tree89b2b0900cf02235741fa670e7947babc8959ebe /shared-core/nv50_fifo.c
parent0055fd5c35306a6363b0414f7f2220b3d1c27ecc (diff)
parente349b58b4a6ebfe299720cb921039a600c145e65 (diff)
Merge branch 'origin' into bo-set-pin
Diffstat (limited to 'shared-core/nv50_fifo.c')
-rw-r--r--shared-core/nv50_fifo.c36
1 files changed, 14 insertions, 22 deletions
diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c
index 71b89d6d..7859544a 100644
--- a/shared-core/nv50_fifo.c
+++ b/shared-core/nv50_fifo.c
@@ -63,24 +63,17 @@ nv50_fifo_channel_enable(struct drm_device *dev, int channel, int nt)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_channel *chan = dev_priv->fifos[channel];
+ uint32_t inst;
DRM_DEBUG("ch%d\n", channel);
- if (IS_G80) {
- if (!chan->ramin)
- return -EINVAL;
-
- NV_WRITE(NV50_PFIFO_CTX_TABLE(channel),
- (chan->ramin->instance >> 12) |
- NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED);
- } else {
- if (!chan->ramfc)
- return -EINVAL;
+ if (!chan->ramfc)
+ return -EINVAL;
- NV_WRITE(NV50_PFIFO_CTX_TABLE(channel),
- (chan->ramfc->instance >> 8) |
- NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED);
- }
+ if (IS_G80) inst = chan->ramfc->instance >> 12;
+ else inst = chan->ramfc->instance >> 8;
+ NV_WRITE(NV50_PFIFO_CTX_TABLE(channel),
+ inst | NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED);
if (!nt) nv50_fifo_init_thingo(dev);
return 0;
@@ -90,16 +83,13 @@ static void
nv50_fifo_channel_disable(struct drm_device *dev, int channel, int nt)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
+ uint32_t inst;
DRM_DEBUG("ch%d, nt=%d\n", channel, nt);
- if (IS_G80) {
- NV_WRITE(NV50_PFIFO_CTX_TABLE(channel),
- NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80);
- } else {
- NV_WRITE(NV50_PFIFO_CTX_TABLE(channel),
- NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84);
- }
+ if (IS_G80) inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80;
+ else inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84;
+ NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), inst);
if (!nt) nv50_fifo_init_thingo(dev);
}
@@ -234,7 +224,9 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
if (IS_G80) {
uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start;
- if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, ~0, 0x100,
+ uint32_t vram_offset = chan->ramin->gpuobj->im_backing->start;
+ if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset,
+ vram_offset, 0x100,
NVOBJ_FLAG_ZERO_ALLOC |
NVOBJ_FLAG_ZERO_FREE,
&ramfc, &chan->ramfc)))