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authorEric Anholt <eric@anholt.net>2007-03-30 12:56:08 -0700
committerEric Anholt <eric@anholt.net>2007-03-30 12:56:08 -0700
commitcd4c82176f3f429e722ca3fac2abf231af479780 (patch)
tree6c658f8ea8cbfcdbb5d3c8518a5f13ca90b465e3 /shared-core/nv40_mc.c
parent5d69640a6ad15522fa37c3b232eb34acef955892 (diff)
parent3f70518f0bcf36a1e2c82db962324dbdee106f67 (diff)
Merge branch 'origin'
Diffstat (limited to 'shared-core/nv40_mc.c')
-rw-r--r--shared-core/nv40_mc.c36
1 files changed, 36 insertions, 0 deletions
diff --git a/shared-core/nv40_mc.c b/shared-core/nv40_mc.c
new file mode 100644
index 00000000..554a2241
--- /dev/null
+++ b/shared-core/nv40_mc.c
@@ -0,0 +1,36 @@
+#include "drmP.h"
+#include "drm.h"
+#include "nouveau_drv.h"
+#include "nouveau_drm.h"
+
+int
+nv40_mc_init(drm_device_t *dev)
+{
+ drm_nouveau_private_t *dev_priv = dev->dev_private;
+ uint32_t tmp;
+
+ NV_WRITE(NV03_PMC_INTR_EN_0, 0);
+
+ switch (dev_priv->chipset) {
+ case 0x44:
+ case 0x46: /* G72 */
+ case 0x4e:
+ case 0x4c: /* C51_G7X */
+ tmp = NV_READ(NV40_PFB_020C);
+ NV_WRITE(NV40_PMC_1700, tmp);
+ NV_WRITE(NV40_PMC_1704, 0);
+ NV_WRITE(NV40_PMC_1708, 0);
+ NV_WRITE(NV40_PMC_170C, tmp);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+void
+nv40_mc_takedown(drm_device_t *dev)
+{
+}
+