diff options
| author | Ben Skeggs <skeggsb@gmail.com> | 2007-07-05 00:12:33 +1000 |
|---|---|---|
| committer | Ben Skeggs <skeggsb@gmail.com> | 2007-07-09 16:16:44 +1000 |
| commit | c806bba4665bb369168ee0b453fa28e2e0bf2a5d (patch) | |
| tree | c3ded5cfc4048301654769a6fa224c3abb57c707 /shared-core/nv40_fifo.c | |
| parent | 3324342e42b78aef8e90e11273776dd2b3b92074 (diff) | |
nouveau/nv50: Initial channel/object support
Should be OK on G84 for a single channel, multiple channels *almost* work.
Untested on G80.
Diffstat (limited to 'shared-core/nv40_fifo.c')
| -rw-r--r-- | shared-core/nv40_fifo.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/shared-core/nv40_fifo.c b/shared-core/nv40_fifo.c index eed3e45b..818a9024 100644 --- a/shared-core/nv40_fifo.c +++ b/shared-core/nv40_fifo.c @@ -40,7 +40,7 @@ int nv40_fifo_create_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; int ret; if ((ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(channel), @@ -67,6 +67,8 @@ nv40_fifo_create_context(drm_device_t *dev, int channel) RAMFC_WR(GRCTX_INSTANCE, chan->ramin_grctx->instance >> 4); RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF); + /* enable the fifo dma operation */ + NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<channel)); return 0; } @@ -74,7 +76,9 @@ void nv40_fifo_destroy_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; + + NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<channel)); if (chan->ramfc) nouveau_gpuobj_ref_del(dev, &chan->ramfc); @@ -84,7 +88,7 @@ int nv40_fifo_load_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp, tmp2; NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET)); @@ -143,7 +147,7 @@ int nv40_fifo_save_context(drm_device_t *dev, int channel) { drm_nouveau_private_t *dev_priv = dev->dev_private; - struct nouveau_fifo *chan = &dev_priv->fifos[channel]; + struct nouveau_fifo *chan = dev_priv->fifos[channel]; uint32_t tmp; RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); |