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authorEric Anholt <eric@anholt.net>2007-03-30 12:56:08 -0700
committerEric Anholt <eric@anholt.net>2007-03-30 12:56:08 -0700
commitcd4c82176f3f429e722ca3fac2abf231af479780 (patch)
tree6c658f8ea8cbfcdbb5d3c8518a5f13ca90b465e3 /shared-core/nv20_graph.c
parent5d69640a6ad15522fa37c3b232eb34acef955892 (diff)
parent3f70518f0bcf36a1e2c82db962324dbdee106f67 (diff)
Merge branch 'origin'
Diffstat (limited to 'shared-core/nv20_graph.c')
-rw-r--r--shared-core/nv20_graph.c79
1 files changed, 79 insertions, 0 deletions
diff --git a/shared-core/nv20_graph.c b/shared-core/nv20_graph.c
index 9ba6a873..45d88d6b 100644
--- a/shared-core/nv20_graph.c
+++ b/shared-core/nv20_graph.c
@@ -136,6 +136,12 @@ int nv20_graph_init(drm_device_t *dev) {
drm_nouveau_private_t *dev_priv =
(drm_nouveau_private_t *)dev->dev_private;
int i;
+ uint32_t tmp, vramsz;
+
+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
+ ~NV_PMC_ENABLE_PGRAPH);
+ NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
+ NV_PMC_ENABLE_PGRAPH);
/* Create Context Pointer Table */
dev_priv->ctx_table_size = 32 * 4;
@@ -151,5 +157,78 @@ int nv20_graph_init(drm_device_t *dev) {
//XXX need to be done and save/restore for each fifo ???
nv20_graph_rdi(dev);
+ NV_WRITE(NV03_PGRAPH_INTR_EN, 0x00000000);
+ NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF);
+
+ NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
+ NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000);
+ NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700);
+ NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xF20E0431);
+ NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000);
+ NV_WRITE(0x40009C , 0x00000040);
+
+ if (dev_priv->chipset >= 0x25) {
+ NV_WRITE(0x400890, 0x00080000);
+ NV_WRITE(0x400610, 0x304B1FB6);
+ NV_WRITE(0x400B80, 0x18B82880);
+ NV_WRITE(0x400B84, 0x44000000);
+ NV_WRITE(0x400098, 0x40000080);
+ NV_WRITE(0x400B88, 0x000000ff);
+ } else {
+ NV_WRITE(0x400880, 0x00080000);
+ NV_WRITE(0x400094, 0x00000005);
+ NV_WRITE(0x400B80, 0x45CAA208);
+ NV_WRITE(0x400B84, 0x24000000);
+ NV_WRITE(0x400098, 0x00000040);
+ NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00038);
+ NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030);
+ NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E10038);
+ NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030);
+ }
+
+ /* copy tile info from PFB */
+ for (i=0; i<NV10_PFB_TILE__SIZE; i++) {
+ NV_WRITE(NV10_PGRAPH_TILE(i), NV_READ(NV10_PFB_TILE(i)));
+ NV_WRITE(NV10_PGRAPH_TLIMIT(i), NV_READ(NV10_PFB_TLIMIT(i)));
+ NV_WRITE(NV10_PGRAPH_TSIZE(i), NV_READ(NV10_PFB_TSIZE(i)));
+ NV_WRITE(NV10_PGRAPH_TSTATUS(i), NV_READ(NV10_PFB_TSTATUS(i)));
+ }
+
+ NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100);
+ NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF);
+ NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001);
+
+ tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
+ NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
+ tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;
+ NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
+
+ /* begin RAM config */
+ vramsz = drm_get_resource_len(dev, 0) - 1;
+ NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0));
+ NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1));
+ NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
+ NV_WRITE(NV10_PGRAPH_RDI_DATA , NV_READ(NV04_PFB_CFG0));
+ NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
+ NV_WRITE(NV10_PGRAPH_RDI_DATA , NV_READ(NV04_PFB_CFG1));
+ NV_WRITE(0x400820, 0);
+ NV_WRITE(0x400824, 0);
+ NV_WRITE(0x400864, vramsz-1);
+ NV_WRITE(0x400868, vramsz-1);
+
+ /* interesting.. the below overwrites some of the tile setup above.. */
+ NV_WRITE(0x400B20, 0x00000000);
+ NV_WRITE(0x400B04, 0xFFFFFFFF);
+
+ NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
+ NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
+ NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
+ NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
+
return 0;
}
+
+void nv20_graph_takedown(drm_device_t *dev)
+{
+}
+