diff options
| author | Ben Skeggs <skeggsb@gmail.com> | 2007-06-25 15:42:55 +1000 |
|---|---|---|
| committer | Ben Skeggs <skeggsb@gmail.com> | 2007-06-28 03:26:44 +1000 |
| commit | 68ecf61647e9ec16d59cc8f50550d11478eb3118 (patch) | |
| tree | 1b1be7d1eb47541c87545013e1405a6925b3013e /shared-core/nv10_fifo.c | |
| parent | 18a6d1c9c380b6b19524f654d9173a79e19aa1df (diff) | |
nouveau: never touch PRAMIN with NV_WRITE, cleanup RAMHT code a bit
Diffstat (limited to 'shared-core/nv10_fifo.c')
| -rw-r--r-- | shared-core/nv10_fifo.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/shared-core/nv10_fifo.c b/shared-core/nv10_fifo.c index 8dad45aa..710a47f7 100644 --- a/shared-core/nv10_fifo.c +++ b/shared-core/nv10_fifo.c @@ -28,8 +28,8 @@ #include "drm.h" #include "nouveau_drv.h" -#define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV10_RAMFC_##offset, (val)) -#define RAMFC_RD(offset) NV_READ (fifoctx + NV10_RAMFC_##offset) +#define RAMFC_WR(offset, val) NV_WI32(fifoctx + NV10_RAMFC_##offset, (val)) +#define RAMFC_RD(offset) NV_RI32(fifoctx + NV10_RAMFC_##offset) #define NV10_FIFO_CONTEXT_SIZE 64 int @@ -42,9 +42,9 @@ nv10_fifo_create_context(drm_device_t *dev, int channel) pushbuf = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance); - fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64; + fifoctx = dev_priv->ramfc_offset + channel*64; for (i=0; i<NV10_FIFO_CONTEXT_SIZE;i+=4) - NV_WRITE(fifoctx + i, 0); + NV_WI32(fifoctx + i, 0); /* Fill entries that are seen filled in dumps of nvidia driver just * after channel's is put into DMA mode @@ -70,9 +70,9 @@ nv10_fifo_destroy_context(drm_device_t *dev, int channel) uint32_t fifoctx; int i; - fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64; + fifoctx = dev_priv->ramfc_offset + channel*64; for (i=0; i<NV10_FIFO_CONTEXT_SIZE;i+=4) - NV_WRITE(fifoctx + i, 0); + NV_WI32(fifoctx + i, 0); } int @@ -82,7 +82,7 @@ nv10_fifo_load_context(drm_device_t *dev, int channel) uint32_t fifoctx; uint32_t tmp; - fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64; + fifoctx = dev_priv->ramfc_offset + channel*64; NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00000100 | channel); @@ -118,7 +118,7 @@ nv10_fifo_save_context(drm_device_t *dev, int channel) uint32_t fifoctx; uint32_t tmp; - fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64; + fifoctx = dev_priv->ramfc_offset + channel*64; RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)); RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET)); |