diff options
| author | Stephane Marchesin <marchesin@icps.u-strasbg.fr> | 2007-02-06 01:17:32 +0100 |
|---|---|---|
| committer | Stephane Marchesin <marchesin@icps.u-strasbg.fr> | 2007-02-06 01:17:32 +0100 |
| commit | 17985f07d68322519919a7f629a6d2d9bf3916ed (patch) | |
| tree | 969c2db6c77420aaed654a15265715becd3ef622 /shared-core/nv04_graph.c | |
| parent | 8c663b4e56b45d377a5a0fed4318a129fc1233fa (diff) | |
nouveau: more work on the nv04 context switch code.
Diffstat (limited to 'shared-core/nv04_graph.c')
| -rw-r--r-- | shared-core/nv04_graph.c | 27 |
1 files changed, 12 insertions, 15 deletions
diff --git a/shared-core/nv04_graph.c b/shared-core/nv04_graph.c index d7d78001..830d673e 100644 --- a/shared-core/nv04_graph.c +++ b/shared-core/nv04_graph.c @@ -29,7 +29,7 @@ struct reg_interval { - int reg; + uint32_t reg; int number; } nv04_graph_ctx_regs [] = { {NV04_PGRAPH_CTX_SWITCH1, 1}, @@ -160,12 +160,10 @@ void nouveau_nv04_context_switch(drm_device_t *dev) DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel); + NV_WRITE(NV03_PFIFO_CACHES, 0x0); + NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0); + NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0); NV_WRITE(NV04_PGRAPH_FIFO,0x0); -#if 0 - NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000); - NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000); - NV_WRITE(NV_PFIFO_CACHES, 0x00000000); -#endif // save PGRAPH context index=0; @@ -178,8 +176,8 @@ void nouveau_nv04_context_switch(drm_device_t *dev) nouveau_wait_for_idle(dev); - NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10000000); - NV_WRITE(NV04_PGRAPH_CTX_USER, (NV_READ(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24)); + NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10000000); + NV_WRITE(NV04_PGRAPH_CTX_USER, (NV_READ(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x0f << 24)); nouveau_wait_for_idle(dev); // restore PGRAPH context @@ -195,15 +193,14 @@ void nouveau_nv04_context_switch(drm_device_t *dev) nouveau_wait_for_idle(dev); #endif - NV_WRITE(NV03_PGRAPH_CTX_CONTROL, 0x10010100); + NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100); NV_WRITE(NV04_PGRAPH_CTX_USER, channel << 24); NV_WRITE(NV04_PGRAPH_FFINTFC_ST2, NV_READ(NV04_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF); -#if 0 - NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001); - NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001); - NV_WRITE(NV_PFIFO_CACHES, 0x00000001); -#endif + NV_WRITE(NV04_PGRAPH_FIFO,0x0); + NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0); + NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x1); + NV_WRITE(NV03_PFIFO_CACHES, 0x1); NV_WRITE(NV04_PGRAPH_FIFO,0x1); } @@ -231,7 +228,7 @@ int nv04_graph_init(drm_device_t *dev) { for ( i = 0 ; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++) sum+=nv04_graph_ctx_regs[i].number; if ( sum*4>sizeof(dev_priv->fifos[0].pgraph_ctx) ) - DRM_ERROR(); + DRM_ERROR("pgraph_ctx too small\n"); return 0; } |