Lindent of core build. Drivers checked for no binary diffs. A few files

    weren't Lindent's because their comments didn't convert very well. A
    bunch of other minor clean up with no code implact included.

1 files changed, 205 insertions, 215 deletions

diff --git a/shared-core/mach64_drv.h b/shared-core/mach64_drv.h
index f047b7ef..698a6a51 100644
--- a/shared-core/mach64_drv.h
+++ b/shared-core/mach64_drv.h
@@ -49,45 +49,45 @@
 
 /* FIXME: remove these when not needed */
 /* Development driver options */
-#define MACH64_EXTRA_CHECKING     0 /* Extra sanity checks for DMA/freelist management */
-#define MACH64_VERBOSE		  0 /* Verbose debugging output */
+#define MACH64_EXTRA_CHECKING     0	/* Extra sanity checks for DMA/freelist management */
+#define MACH64_VERBOSE		  0	/* Verbose debugging output */
 
 typedef struct drm_mach64_freelist {
-	struct list_head  list;  /* List pointers for free_list, placeholders, or pending list */
-   	drm_buf_t *buf;          /* Pointer to the buffer */
-	int discard;             /* This flag is set when we're done (re)using a buffer */
-	u32 ring_ofs;            /* dword offset in ring of last descriptor for this buffer */
+	struct list_head list;	/* List pointers for free_list, placeholders, or pending list */
+	drm_buf_t *buf;		/* Pointer to the buffer */
+	int discard;		/* This flag is set when we're done (re)using a buffer */
+	u32 ring_ofs;		/* dword offset in ring of last descriptor for this buffer */
 } drm_mach64_freelist_t;
 
 typedef struct drm_mach64_descriptor_ring {
-	dma_addr_t handle;       /* handle (bus address) of ring returned by pci_alloc_consistent() */
-	void *start;             /* write pointer (cpu address) to start of descriptor ring */
-	u32 start_addr;          /* bus address of beginning of descriptor ring */
-       	int size;                /* size of ring in bytes */
-
-	u32 head_addr;           /* bus address of descriptor ring head */
-	u32 head;                /* dword offset of descriptor ring head */
-	u32 tail;                /* dword offset of descriptor ring tail */
-	u32 tail_mask;           /* mask used to wrap ring */
-	int space;               /* number of free bytes in ring */
+	dma_addr_t handle;	/* handle (bus address) of ring returned by pci_alloc_consistent() */
+	void *start;		/* write pointer (cpu address) to start of descriptor ring */
+	u32 start_addr;		/* bus address of beginning of descriptor ring */
+	int size;		/* size of ring in bytes */
+
+	u32 head_addr;		/* bus address of descriptor ring head */
+	u32 head;		/* dword offset of descriptor ring head */
+	u32 tail;		/* dword offset of descriptor ring tail */
+	u32 tail_mask;		/* mask used to wrap ring */
+	int space;		/* number of free bytes in ring */
 } drm_mach64_descriptor_ring_t;
 
 typedef struct drm_mach64_private {
 	drm_mach64_sarea_t *sarea_priv;
 
 	int is_pci;
-	drm_mach64_dma_mode_t driver_mode;       /* Async DMA, sync DMA, or MMIO */
+	drm_mach64_dma_mode_t driver_mode;	/* Async DMA, sync DMA, or MMIO */
 
-	int usec_timeout;                        /* Timeout for the wait functions */
+	int usec_timeout;	/* Timeout for the wait functions */
 
-	drm_mach64_descriptor_ring_t ring;       /* DMA descriptor table (ring buffer) */
-	int ring_running;                        /* Is bus mastering is enabled */
+	drm_mach64_descriptor_ring_t ring;	/* DMA descriptor table (ring buffer) */
+	int ring_running;	/* Is bus mastering is enabled */
 
-	struct list_head free_list;              /* Free-list head */
-	struct list_head placeholders;           /* Placeholder list for buffers held by clients */
-	struct list_head pending;                /* Buffers pending completion */
+	struct list_head free_list;	/* Free-list head */
+	struct list_head placeholders;	/* Placeholder list for buffers held by clients */
+	struct list_head pending;	/* Buffers pending completion */
 
-	u32 frame_ofs[MACH64_MAX_QUEUED_FRAMES]; /* dword ring offsets of most recent frame swaps */
+	u32 frame_ofs[MACH64_MAX_QUEUED_FRAMES];	/* dword ring offsets of most recent frame swaps */
 
 	unsigned int fb_bpp;
 	unsigned int front_offset, front_pitch;
@@ -104,48 +104,49 @@ typedef struct drm_mach64_private {
 	drm_local_map_t *fb;
 	drm_local_map_t *mmio;
 	drm_local_map_t *ring_map;
-	drm_local_map_t *dev_buffers; /* this is a pointer to a structure in dev */
+	drm_local_map_t *dev_buffers;	/* this is a pointer to a structure in dev */
 	drm_local_map_t *agp_textures;
 } drm_mach64_private_t;
 
 				/* mach64_dma.c */
-extern int mach64_dma_init( DRM_IOCTL_ARGS );
-extern int mach64_dma_idle( DRM_IOCTL_ARGS );
-extern int mach64_dma_flush( DRM_IOCTL_ARGS );
-extern int mach64_engine_reset( DRM_IOCTL_ARGS );
-extern int mach64_dma_buffers( DRM_IOCTL_ARGS );
-extern void mach64_driver_pretakedown(drm_device_t *dev);
-
-extern int mach64_init_freelist( drm_device_t *dev );
-extern void mach64_destroy_freelist( drm_device_t *dev );
-extern drm_buf_t *mach64_freelist_get( drm_mach64_private_t *dev_priv );
-
-extern int mach64_do_wait_for_fifo( drm_mach64_private_t *dev_priv,
-				    int entries );
-extern int mach64_do_wait_for_idle( drm_mach64_private_t *dev_priv );
-extern int mach64_wait_ring( drm_mach64_private_t *dev_priv, int n );
-extern int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv );
-extern int mach64_do_release_used_buffers( drm_mach64_private_t *dev_priv );
-extern void mach64_dump_engine_info( drm_mach64_private_t *dev_priv );
-extern void mach64_dump_ring_info( drm_mach64_private_t *dev_priv );
-extern int mach64_do_engine_reset( drm_mach64_private_t *dev_priv );
-
-extern int mach64_do_dma_idle( drm_mach64_private_t *dev_priv );
-extern int mach64_do_dma_flush( drm_mach64_private_t *dev_priv );
-extern int mach64_do_cleanup_dma( drm_device_t *dev );
+extern int mach64_dma_init(DRM_IOCTL_ARGS);
+extern int mach64_dma_idle(DRM_IOCTL_ARGS);
+extern int mach64_dma_flush(DRM_IOCTL_ARGS);
+extern int mach64_engine_reset(DRM_IOCTL_ARGS);
+extern int mach64_dma_buffers(DRM_IOCTL_ARGS);
+extern void mach64_driver_pretakedown(drm_device_t * dev);
+
+extern int mach64_init_freelist(drm_device_t * dev);
+extern void mach64_destroy_freelist(drm_device_t * dev);
+extern drm_buf_t *mach64_freelist_get(drm_mach64_private_t * dev_priv);
+
+extern int mach64_do_wait_for_fifo(drm_mach64_private_t * dev_priv,
+				   int entries);
+extern int mach64_do_wait_for_idle(drm_mach64_private_t * dev_priv);
+extern int mach64_wait_ring(drm_mach64_private_t * dev_priv, int n);
+extern int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t * dev_priv);
+extern int mach64_do_release_used_buffers(drm_mach64_private_t * dev_priv);
+extern void mach64_dump_engine_info(drm_mach64_private_t * dev_priv);
+extern void mach64_dump_ring_info(drm_mach64_private_t * dev_priv);
+extern int mach64_do_engine_reset(drm_mach64_private_t * dev_priv);
+
+extern int mach64_do_dma_idle(drm_mach64_private_t * dev_priv);
+extern int mach64_do_dma_flush(drm_mach64_private_t * dev_priv);
+extern int mach64_do_cleanup_dma(drm_device_t * dev);
 
 				/* mach64_state.c */
-extern int mach64_dma_clear( DRM_IOCTL_ARGS );
-extern int mach64_dma_swap( DRM_IOCTL_ARGS );
-extern int mach64_dma_vertex( DRM_IOCTL_ARGS );
-extern int mach64_dma_blit( DRM_IOCTL_ARGS );
-extern int mach64_get_param( DRM_IOCTL_ARGS );
-extern int mach64_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
-
-extern irqreturn_t mach64_driver_irq_handler( DRM_IRQ_ARGS );
-extern void mach64_driver_irq_preinstall( drm_device_t *dev );
-extern void mach64_driver_irq_postinstall( drm_device_t *dev );
-extern void mach64_driver_irq_uninstall( drm_device_t *dev );
+extern int mach64_dma_clear(DRM_IOCTL_ARGS);
+extern int mach64_dma_swap(DRM_IOCTL_ARGS);
+extern int mach64_dma_vertex(DRM_IOCTL_ARGS);
+extern int mach64_dma_blit(DRM_IOCTL_ARGS);
+extern int mach64_get_param(DRM_IOCTL_ARGS);
+extern int mach64_driver_vblank_wait(drm_device_t * dev,
+				     unsigned int *sequence);
+
+extern irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS);
+extern void mach64_driver_irq_preinstall(drm_device_t * dev);
+extern void mach64_driver_irq_postinstall(drm_device_t * dev);
+extern void mach64_driver_irq_uninstall(drm_device_t * dev);
 
 /* ================================================================
  * Registers
@@ -155,7 +156,6 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev );
 #define MACH64_AGP_CNTL				0x014c
 #define MACH64_ALPHA_TST_CNTL			0x0550
 
-
 #define MACH64_DSP_CONFIG 			0x0420
 #define MACH64_DSP_ON_OFF 			0x0424
 #define MACH64_EXT_MEM_CNTL 			0x04ac
@@ -165,7 +165,6 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev );
 #define MACH64_MEM_BUF_CNTL 			0x042c
 #define MACH64_MEM_CNTL 			0x04b0
 
-
 #define MACH64_BM_ADDR				0x0648
 #define MACH64_BM_COMMAND			0x0188
 #define MACH64_BM_DATA				0x0648
@@ -390,17 +389,17 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev );
 #	define MACH64_CRTC_VBLANK_INT			(1 << 2)
 #	define MACH64_CRTC_VLINE_INT_EN			(1 << 3)
 #	define MACH64_CRTC_VLINE_INT			(1 << 4)
-#	define MACH64_CRTC_VLINE_SYNC			(1 << 5) /* 0=even, 1=odd */
-#	define MACH64_CRTC_FRAME			(1 << 6) /* 0=even, 1=odd */
+#	define MACH64_CRTC_VLINE_SYNC			(1 << 5)	/* 0=even, 1=odd */
+#	define MACH64_CRTC_FRAME			(1 << 6)	/* 0=even, 1=odd */
 #	define MACH64_CRTC_SNAPSHOT_INT_EN		(1 << 7)
 #	define MACH64_CRTC_SNAPSHOT_INT			(1 << 8)
 #	define MACH64_CRTC_I2C_INT_EN			(1 << 9)
 #	define MACH64_CRTC_I2C_INT			(1 << 10)
-#	define MACH64_CRTC2_VBLANK			(1 << 11) /* LT Pro */
-#	define MACH64_CRTC2_VBLANK_INT_EN		(1 << 12) /* LT Pro */
-#	define MACH64_CRTC2_VBLANK_INT			(1 << 13) /* LT Pro */
-#	define MACH64_CRTC2_VLINE_INT_EN		(1 << 14) /* LT Pro */
-#	define MACH64_CRTC2_VLINE_INT			(1 << 15) /* LT Pro */
+#	define MACH64_CRTC2_VBLANK			(1 << 11)	/* LT Pro */
+#	define MACH64_CRTC2_VBLANK_INT_EN		(1 << 12)	/* LT Pro */
+#	define MACH64_CRTC2_VBLANK_INT			(1 << 13)	/* LT Pro */
+#	define MACH64_CRTC2_VLINE_INT_EN		(1 << 14)	/* LT Pro */
+#	define MACH64_CRTC2_VLINE_INT			(1 << 15)	/* LT Pro */
 #	define MACH64_CRTC_CAPBUF0_INT_EN		(1 << 16)
 #	define MACH64_CRTC_CAPBUF0_INT			(1 << 17)
 #	define MACH64_CRTC_CAPBUF1_INT_EN		(1 << 18)
@@ -413,9 +412,9 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev );
 #	define MACH64_CRTC_BUSMASTER_EOL_INT		(1 << 25)
 #	define MACH64_CRTC_GP_INT_EN			(1 << 26)
 #	define MACH64_CRTC_GP_INT			(1 << 27)
-#	define MACH64_CRTC2_VLINE_SYNC			(1 << 28) /* LT Pro */  /* 0=even, 1=odd */
-#	define MACH64_CRTC_SNAPSHOT2_INT_EN		(1 << 29) /* LT Pro */
-#	define MACH64_CRTC_SNAPSHOT2_INT		(1 << 30) /* LT Pro */
+#	define MACH64_CRTC2_VLINE_SYNC			(1 << 28) /* LT Pro */	/* 0=even, 1=odd */
+#	define MACH64_CRTC_SNAPSHOT2_INT_EN		(1 << 29)	/* LT Pro */
+#	define MACH64_CRTC_SNAPSHOT2_INT		(1 << 30)	/* LT Pro */
 #	define MACH64_CRTC_VBLANK2_INT			(1 << 31)
 #	define MACH64_CRTC_INT_ENS				\
 		(						\
@@ -468,7 +467,6 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev );
 #define MACH64_READ(reg)	DRM_READ32(dev_priv->mmio, (reg) )
 #define MACH64_WRITE(reg,val)	DRM_WRITE32(dev_priv->mmio, (reg), (val) )
 
-
 #define DWMREG0		0x0400
 #define DWMREG0_END	0x07ff
 #define DWMREG1		0x0000
@@ -492,254 +490,246 @@ extern void mach64_driver_irq_uninstall( drm_device_t *dev );
  */
 
 /* DMA descriptor field indices:
- * The descriptor fields are loaded into the read-only 
+ * The descriptor fields are loaded into the read-only
  * BM_* system bus master registers during a bus-master operation
  */
-#define MACH64_DMA_FRAME_BUF_OFFSET	0        /* BM_FRAME_BUF_OFFSET */
-#define MACH64_DMA_SYS_MEM_ADDR		1        /* BM_SYSTEM_MEM_ADDR */
-#define MACH64_DMA_COMMAND		2        /* BM_COMMAND */
-#define MACH64_DMA_RESERVED		3        /* BM_STATUS */
+#define MACH64_DMA_FRAME_BUF_OFFSET	0	/* BM_FRAME_BUF_OFFSET */
+#define MACH64_DMA_SYS_MEM_ADDR		1	/* BM_SYSTEM_MEM_ADDR */
+#define MACH64_DMA_COMMAND		2	/* BM_COMMAND */
+#define MACH64_DMA_RESERVED		3	/* BM_STATUS */
 
 /* BM_COMMAND descriptor field flags */
-#define MACH64_DMA_HOLD_OFFSET		(1<<30)  /* Don't increment DMA_FRAME_BUF_OFFSET */
-#define MACH64_DMA_EOL			(1<<31)  /* End of descriptor list flag */
-
-#define MACH64_DMA_CHUNKSIZE	        0x1000   /* 4kB per DMA descriptor */
-#define MACH64_APERTURE_OFFSET	        0x7ff800 /* frame-buffer offset for gui-masters */
+#define MACH64_DMA_HOLD_OFFSET		(1<<30)	/* Don't increment DMA_FRAME_BUF_OFFSET */
+#define MACH64_DMA_EOL			(1<<31)	/* End of descriptor list flag */
 
+#define MACH64_DMA_CHUNKSIZE	        0x1000	/* 4kB per DMA descriptor */
+#define MACH64_APERTURE_OFFSET	        0x7ff800	/* frame-buffer offset for gui-masters */
 
 /* ================================================================
  * Misc helper macros
  */
 
-static __inline__ void mach64_set_dma_eol( volatile u32 * addr )
+static __inline__ void mach64_set_dma_eol(volatile u32 * addr)
 {
 #if defined(__i386__)
 	int nr = 31;
-	
+
 	/* Taken from include/asm-i386/bitops.h linux header */
-        __asm__ __volatile__( "lock;"
-                "btsl %1,%0"
-                :"=m" (*addr)
-                :"Ir" (nr));
+	__asm__ __volatile__("lock;" "btsl %1,%0":"=m"(*addr)
+			     :"Ir"(nr));
 #elif defined(__powerpc__)
 	u32 old;
-	u32 mask = cpu_to_le32( MACH64_DMA_EOL );
+	u32 mask = cpu_to_le32(MACH64_DMA_EOL);
 
 	/* Taken from the include/asm-ppc/bitops.h linux header */
 	__asm__ __volatile__("\n\
 1:	lwarx	%0,0,%3 \n\
 	or	%0,%0,%2 \n\
 	stwcx.	%0,0,%3 \n\
-	bne-	1b"
-	: "=&r" (old), "=m" (*addr)
-	: "r" (mask), "r" (addr), "m" (*addr)
-	: "cc");
+	bne-	1b":"=&r"(old), "=m"(*addr)
+			     :"r"(mask), "r"(addr), "m"(*addr)
+			     :"cc");
 #elif defined(__alpha__)
 	u32 temp;
 	u32 mask = MACH64_DMA_EOL;
 
 	/* Taken from the include/asm-alpha/bitops.h linux header */
-	__asm__ __volatile__(
-	"1:	ldl_l %0,%3\n"
-	"	bis %0,%2,%0\n"
-	"	stl_c %0,%1\n"
-	"	beq %0,2f\n"
-	".subsection 2\n"
-	"2:	br 1b\n"
-	".previous"
-	:"=&r" (temp), "=m" (*addr)
-	:"Ir" (mask), "m" (*addr));
+	__asm__ __volatile__("1:	ldl_l %0,%3\n"
+			     "	bis %0,%2,%0\n"
+			     "	stl_c %0,%1\n"
+			     "	beq %0,2f\n"
+			     ".subsection 2\n"
+			     "2:	br 1b\n"
+			     ".previous":"=&r"(temp), "=m"(*addr)
+			     :"Ir"(mask), "m"(*addr));
 #else
-	u32 mask = cpu_to_le32( MACH64_DMA_EOL );
+	u32 mask = cpu_to_le32(MACH64_DMA_EOL);
 
 	*addr |= mask;
 #endif
 }
 
-static __inline__ void mach64_clear_dma_eol( volatile u32 * addr )
+static __inline__ void mach64_clear_dma_eol(volatile u32 * addr)
 {
 #if defined(__i386__)
 	int nr = 31;
-	
+
 	/* Taken from include/asm-i386/bitops.h linux header */
-        __asm__ __volatile__( "lock;"
-                "btrl %1,%0"
-                :"=m" (*addr)
-                :"Ir" (nr));
+	__asm__ __volatile__("lock;" "btrl %1,%0":"=m"(*addr)
+			     :"Ir"(nr));
 #elif defined(__powerpc__)
 	u32 old;
-	u32 mask = cpu_to_le32( MACH64_DMA_EOL );
+	u32 mask = cpu_to_le32(MACH64_DMA_EOL);
 
 	/* Taken from the include/asm-ppc/bitops.h linux header */
 	__asm__ __volatile__("\n\
 1:	lwarx	%0,0,%3 \n\
 	andc	%0,%0,%2 \n\
 	stwcx.	%0,0,%3 \n\
-	bne-	1b"
-	: "=&r" (old), "=m" (*addr)
-	: "r" (mask), "r" (addr), "m" (*addr)
-	: "cc");
+	bne-	1b":"=&r"(old), "=m"(*addr)
+			     :"r"(mask), "r"(addr), "m"(*addr)
+			     :"cc");
 #elif defined(__alpha__)
 	u32 temp;
 	u32 mask = ~MACH64_DMA_EOL;
 
 	/* Taken from the include/asm-alpha/bitops.h linux header */
-	__asm__ __volatile__(
-	"1:	ldl_l %0,%3\n"
-	"	and %0,%2,%0\n"
-	"	stl_c %0,%1\n"
-	"	beq %0,2f\n"
-	".subsection 2\n"
-	"2:	br 1b\n"
-	".previous"
-	:"=&r" (temp), "=m" (*addr)
-	:"Ir" (mask), "m" (*addr));
+	__asm__ __volatile__("1:	ldl_l %0,%3\n"
+			     "	and %0,%2,%0\n"
+			     "	stl_c %0,%1\n"
+			     "	beq %0,2f\n"
+			     ".subsection 2\n"
+			     "2:	br 1b\n"
+			     ".previous":"=&r"(temp), "=m"(*addr)
+			     :"Ir"(mask), "m"(*addr));
 #else
-	u32 mask = cpu_to_le32( ~MACH64_DMA_EOL );
+	u32 mask = cpu_to_le32(~MACH64_DMA_EOL);
 
 	*addr &= mask;
 #endif
 }
 
-static __inline__ void mach64_ring_start( drm_mach64_private_t *dev_priv )
+static __inline__ void mach64_ring_start(drm_mach64_private_t * dev_priv)
 {
 	drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
-	
-	DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
-		   __FUNCTION__, 
-		   ring->head_addr, ring->head, ring->tail, ring->space );
 
-	if ( mach64_do_wait_for_idle( dev_priv ) < 0 ) {
-		mach64_do_engine_reset( dev_priv );
+	DRM_DEBUG("%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
+		  __FUNCTION__,
+		  ring->head_addr, ring->head, ring->tail, ring->space);
+
+	if (mach64_do_wait_for_idle(dev_priv) < 0) {
+		mach64_do_engine_reset(dev_priv);
 	}
 
-	if (dev_priv->driver_mode != MACH64_MODE_MMIO ) {
+	if (dev_priv->driver_mode != MACH64_MODE_MMIO) {
 		/* enable bus mastering and block 1 registers */
-		MACH64_WRITE( MACH64_BUS_CNTL, 
-			      ( MACH64_READ(MACH64_BUS_CNTL) & 	~MACH64_BUS_MASTER_DIS ) 
-			      | MACH64_BUS_EXT_REG_EN );
-		mach64_do_wait_for_idle( dev_priv );
+		MACH64_WRITE(MACH64_BUS_CNTL,
+			     (MACH64_READ(MACH64_BUS_CNTL) &
+			      ~MACH64_BUS_MASTER_DIS)
+			     | MACH64_BUS_EXT_REG_EN);
+		mach64_do_wait_for_idle(dev_priv);
 	}
-	
+
 	/* reset descriptor table ring head */
-	MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, 
-		      ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB );
-	
+	MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
+		     ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);
+
 	dev_priv->ring_running = 1;
 }
 
-static __inline__ void mach64_ring_resume( drm_mach64_private_t *dev_priv, 
-					   drm_mach64_descriptor_ring_t *ring )
+static __inline__ void mach64_ring_resume(drm_mach64_private_t * dev_priv,
+					  drm_mach64_descriptor_ring_t * ring)
 {
-	DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
-		   __FUNCTION__, 
-		   ring->head_addr, ring->head, ring->tail, ring->space );
+	DRM_DEBUG("%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
+		  __FUNCTION__,
+		  ring->head_addr, ring->head, ring->tail, ring->space);
 
 	/* reset descriptor table ring head */
-	MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, 
-		      ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB );
+	MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
+		     ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);
 
-	if ( dev_priv->driver_mode == MACH64_MODE_MMIO ) {
-		mach64_do_dispatch_pseudo_dma( dev_priv );
+	if (dev_priv->driver_mode == MACH64_MODE_MMIO) {
+		mach64_do_dispatch_pseudo_dma(dev_priv);
 	} else {
 		/* enable GUI bus mastering, and sync the bus master to the GUI */
-		MACH64_WRITE( MACH64_SRC_CNTL, 
-			      MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC |
-			      MACH64_SRC_BM_OP_SYSTEM_TO_REG );
+		MACH64_WRITE(MACH64_SRC_CNTL,
+			     MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC |
+			     MACH64_SRC_BM_OP_SYSTEM_TO_REG);
 
 		/* kick off the transfer */
-		MACH64_WRITE( MACH64_DST_HEIGHT_WIDTH, 0 );
-		if ( dev_priv->driver_mode == MACH64_MODE_DMA_SYNC ) {
-			if ( (mach64_do_wait_for_idle( dev_priv )) < 0 ) {
-				DRM_ERROR( "%s: idle failed, resetting engine\n", 
-					   __FUNCTION__);
-				mach64_dump_engine_info( dev_priv );
-				mach64_do_engine_reset( dev_priv );
+		MACH64_WRITE(MACH64_DST_HEIGHT_WIDTH, 0);
+		if (dev_priv->driver_mode == MACH64_MODE_DMA_SYNC) {
+			if ((mach64_do_wait_for_idle(dev_priv)) < 0) {
+				DRM_ERROR("%s: idle failed, resetting engine\n",
+					  __FUNCTION__);
+				mach64_dump_engine_info(dev_priv);
+				mach64_do_engine_reset(dev_priv);
 				return;
 			}
-			mach64_do_release_used_buffers( dev_priv );
+			mach64_do_release_used_buffers(dev_priv);
 		}
 	}
 }
 
-static __inline__ void mach64_ring_tick( drm_mach64_private_t *dev_priv, 
-					 drm_mach64_descriptor_ring_t *ring )
+static __inline__ void mach64_ring_tick(drm_mach64_private_t * dev_priv,
+					drm_mach64_descriptor_ring_t * ring)
 {
-	DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
-		   __FUNCTION__, 
-		   ring->head_addr, ring->head, ring->tail, ring->space );
-
-	if ( !dev_priv->ring_running ) {
-		mach64_ring_start( dev_priv );
-		
-		if ( ring->head != ring->tail ) {
-			mach64_ring_resume( dev_priv, ring );
+	DRM_DEBUG("%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
+		  __FUNCTION__,
+		  ring->head_addr, ring->head, ring->tail, ring->space);
+
+	if (!dev_priv->ring_running) {
+		mach64_ring_start(dev_priv);
+
+		if (ring->head != ring->tail) {
+			mach64_ring_resume(dev_priv, ring);
 		}
 	} else {
-		/* GUI_ACTIVE must be read before BM_GUI_TABLE to 
-		 * correctly determine the ring head 
+		/* GUI_ACTIVE must be read before BM_GUI_TABLE to
+		 * correctly determine the ring head
 		 */
-		int gui_active = MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE;
-		
+		int gui_active =
+		    MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE;
+
 		ring->head_addr = MACH64_READ(MACH64_BM_GUI_TABLE) & 0xfffffff0;
-		
-		if ( gui_active ) {
-			/* If not idle, BM_GUI_TABLE points one descriptor 
-			 * past the current head 
+
+		if (gui_active) {
+			/* If not idle, BM_GUI_TABLE points one descriptor
+			 * past the current head
 			 */
-			if ( ring->head_addr == ring->start_addr ) {
+			if (ring->head_addr == ring->start_addr) {
 				ring->head_addr += ring->size;
 			}
 			ring->head_addr -= 4 * sizeof(u32);
 		}
 
-		if( ring->head_addr < ring->start_addr || 
-		    ring->head_addr >= ring->start_addr + ring->size ) {
-			DRM_ERROR( "bad ring head address: 0x%08x\n", ring->head_addr );
-			mach64_dump_ring_info( dev_priv );
-			mach64_do_engine_reset( dev_priv );
+		if (ring->head_addr < ring->start_addr ||
+		    ring->head_addr >= ring->start_addr + ring->size) {
+			DRM_ERROR("bad ring head address: 0x%08x\n",
+				  ring->head_addr);
+			mach64_dump_ring_info(dev_priv);
+			mach64_do_engine_reset(dev_priv);
 			return;
 		}
-	
+
 		ring->head = (ring->head_addr - ring->start_addr) / sizeof(u32);
-		
-		if ( !gui_active && ring->head != ring->tail ) {
-			mach64_ring_resume( dev_priv, ring );
+
+		if (!gui_active && ring->head != ring->tail) {
+			mach64_ring_resume(dev_priv, ring);
 		}
 	}
 }
 
-static __inline__ void mach64_ring_stop( drm_mach64_private_t *dev_priv )
+static __inline__ void mach64_ring_stop(drm_mach64_private_t * dev_priv)
 {
-	DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
-		   __FUNCTION__, 
-		   dev_priv->ring.head_addr, dev_priv->ring.head, 
-		   dev_priv->ring.tail, dev_priv->ring.space );
+	DRM_DEBUG("%s: head_addr: 0x%08x head: %d tail: %d space: %d\n",
+		  __FUNCTION__,
+		  dev_priv->ring.head_addr, dev_priv->ring.head,
+		  dev_priv->ring.tail, dev_priv->ring.space);
 
 	/* restore previous SRC_CNTL to disable busmastering */
-	mach64_do_wait_for_fifo( dev_priv, 1 );
-	MACH64_WRITE( MACH64_SRC_CNTL, 0 );
-
-	/* disable busmastering but keep the block 1 registers enabled */ 
-	mach64_do_wait_for_idle( dev_priv );
-	MACH64_WRITE( MACH64_BUS_CNTL, MACH64_READ( MACH64_BUS_CNTL ) 
-		      | MACH64_BUS_MASTER_DIS | MACH64_BUS_EXT_REG_EN );
-		
+	mach64_do_wait_for_fifo(dev_priv, 1);
+	MACH64_WRITE(MACH64_SRC_CNTL, 0);
+
+	/* disable busmastering but keep the block 1 registers enabled */
+	mach64_do_wait_for_idle(dev_priv);
+	MACH64_WRITE(MACH64_BUS_CNTL, MACH64_READ(MACH64_BUS_CNTL)
+		     | MACH64_BUS_MASTER_DIS | MACH64_BUS_EXT_REG_EN);
+
 	dev_priv->ring_running = 0;
 }
 
 static __inline__ void
-mach64_update_ring_snapshot( drm_mach64_private_t *dev_priv )
+mach64_update_ring_snapshot(drm_mach64_private_t * dev_priv)
 {
 	drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
 
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-	
-	mach64_ring_tick( dev_priv, ring );
+	DRM_DEBUG("%s\n", __FUNCTION__);
+
+	mach64_ring_tick(dev_priv, ring);
 
 	ring->space = (ring->head - ring->tail) * sizeof(u32);
-	if ( ring->space <= 0 ) {
+	if (ring->space <= 0) {
 		ring->space += ring->size;
 	}
 }
@@ -797,7 +787,6 @@ do {									\
 	mach64_ring_tick( dev_priv, &(dev_priv)->ring );		\
 } while (0)
 
-
 /* ================================================================
  * DMA macros
  */
@@ -816,9 +805,10 @@ do {									\
 
 #define GETRINGOFFSET() (_entry->ring_ofs)
 
-static __inline__ int mach64_find_pending_buf_entry ( drm_mach64_private_t *dev_priv, 
-						      drm_mach64_freelist_t **entry, 
-						      drm_buf_t *buf )
+static __inline__ int mach64_find_pending_buf_entry(drm_mach64_private_t *
+						    dev_priv,
+						    drm_mach64_freelist_t **
+						    entry, drm_buf_t * buf)
 {
 	struct list_head *ptr;
 #if MACH64_EXTRA_CHECKING
@@ -1050,4 +1040,4 @@ do {											 \
 	ADVANCE_RING();									 \
 } while(0)
 
-#endif /* __MACH64_DRV_H__ */
+#endif				/* __MACH64_DRV_H__ */