diff options
| author | Wang Zhenyu <zhenyu.z.wang@intel.com> | 2007-06-05 11:15:29 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2007-06-05 11:15:29 -0700 |
| commit | 109e2a10f260f3a5f78762bbedcaeb9b2ebde1c0 (patch) | |
| tree | 6b968ef48f9a3592bdcc801d09c58bc0d081ebcf /shared-core/drm_pciids.txt | |
| parent | 5bd0ca125ed687b2dc6896197c0c8ab2673897f8 (diff) | |
Add support for the G33, Q33, and Q35 chipsets.
These require that the status page be referenced by a pointer in GTT, rather
than phsyical memory. So, we have the X Server allocate that memory and tell
us the address, instead.
Diffstat (limited to 'shared-core/drm_pciids.txt')
| -rw-r--r-- | shared-core/drm_pciids.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index 4b07e4f6..ba02aa89 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -289,6 +289,9 @@ 0x8086 0x29A2 CHIP_I9XX|CHIP_I965 "Intel i965G" 0x8086 0x2A02 CHIP_I9XX|CHIP_I965 "Intel i965GM" 0x8086 0x2A12 CHIP_I9XX|CHIP_I965 "Intel i965GME/GLE" +0x8086 0x29C2 CHIP_I9XX|CHIP_I915 "Intel G33" +0x8086 0x29B2 CHIP_I9XX|CHIP_I915 "Intel Q35" +0x8086 0x29D2 CHIP_I9XX|CHIP_I915 "Intel Q33" [imagine] 0x105d 0x2309 IMAGINE_128 "Imagine 128" |