diff options
| author | Michel Dänzer <michel.daenzer@amd.com> | 2014-09-26 18:19:12 +0900 |
|---|---|---|
| committer | Michel Dänzer <michel@daenzer.net> | 2014-09-29 16:50:06 +0900 |
| commit | c866dc7c00e7f5f219901a9a81bf456a24d29cd1 (patch) | |
| tree | e14a994f6f19684f4ed82ae7974fc76fa02c31a2 /radeon | |
| parent | 7068d987f4dc1260a948f2b4782c66d3d80e9978 (diff) | |
radeon: Always multiply pitch_bytes by nsamples, not by slice_pt
slice_pt is tileb[0] / tile_split, which isn't directly related to the
pitch.
This caused pitch_bytes to be too large in some cases.
[0] Tile size in bytes
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Diffstat (limited to 'radeon')
| -rw-r--r-- | radeon/radeon_surface.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 0723425e..930017ef 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -595,7 +595,7 @@ static void eg_surf_minify(struct radeon_surface *surf, mtile_ps = (mtile_pr * surflevel->nblk_y) / mtileh; surflevel->offset = offset; - surflevel->pitch_bytes = surflevel->nblk_x * bpe * slice_pt; + surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; surflevel->slice_size = mtile_ps * mtileb * slice_pt; surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; @@ -1498,7 +1498,7 @@ static void si_surf_minify_2d(struct radeon_surface *surf, /* macro tile per slice */ mtile_ps = (mtile_pr * surflevel->nblk_y) / yalign; surflevel->offset = offset; - surflevel->pitch_bytes = surflevel->nblk_x * bpe * slice_pt; + surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; surflevel->slice_size = mtile_ps * mtileb * slice_pt; surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; |