Merged ati-pcigart-1-0-0

1 files changed, 111 insertions, 94 deletions

diff --git a/linux/radeon_drv.h b/linux/radeon_drv.h
index 06b54199..24935847 100644
--- a/linux/radeon_drv.h
+++ b/linux/radeon_drv.h
@@ -24,10 +24,8 @@
  * DEALINGS IN THE SOFTWARE.
  *
  * Authors:
- *   Rickard E. (Rik) Faith <faith@valinux.com>
- *   Kevin E. Martin <martin@valinux.com>
- *   Gareth Hughes <gareth@valinux.com>
- *
+ *    Kevin E. Martin <martin@valinux.com>
+ *    Gareth Hughes <gareth@valinux.com>
  */
 
 #ifndef __RADEON_DRV_H__
@@ -50,6 +48,8 @@ typedef struct drm_radeon_ring_buffer {
 	u32 tail;
 	u32 tail_mask;
 	int space;
+
+	int high_mark;
 } drm_radeon_ring_buffer_t;
 
 typedef struct drm_radeon_depth_clear_t {
@@ -64,7 +64,7 @@ typedef struct drm_radeon_private {
 
 	int agp_size;
 	u32 agp_vm_start;
-	u32 agp_buffers_offset;
+	unsigned long agp_buffers_offset;
 
 	int cp_mode;
 	int cp_running;
@@ -83,6 +83,7 @@ typedef struct drm_radeon_private {
 
 	int usec_timeout;
 	int is_pci;
+	unsigned long phys_pci_gart;
 
 	atomic_t idle_count;
 
@@ -91,13 +92,13 @@ typedef struct drm_radeon_private {
 	u32 crtc_offset;
 	u32 crtc_offset_cntl;
 
-	unsigned int color_fmt;
+	u32 color_fmt;
 	unsigned int front_offset;
 	unsigned int front_pitch;
 	unsigned int back_offset;
 	unsigned int back_pitch;
 
-	unsigned int depth_fmt;
+	u32 depth_fmt;
 	unsigned int depth_offset;
 	unsigned int depth_pitch;
 
@@ -124,18 +125,6 @@ typedef struct drm_radeon_buf_priv {
    	drm_radeon_freelist_t *list_entry;
 } drm_radeon_buf_priv_t;
 
-				/* radeon_drv.c */
-extern int  radeon_version( struct inode *inode, struct file *filp,
-			    unsigned int cmd, unsigned long arg );
-extern int  radeon_open( struct inode *inode, struct file *filp );
-extern int  radeon_release( struct inode *inode, struct file *filp );
-extern int  radeon_ioctl( struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg );
-extern int  radeon_lock( struct inode *inode, struct file *filp,
-			 unsigned int cmd, unsigned long arg );
-extern int  radeon_unlock( struct inode *inode, struct file *filp,
-			   unsigned int cmd, unsigned long arg );
-
 				/* radeon_cp.c */
 extern int radeon_cp_init( struct inode *inode, struct file *filp,
 			   unsigned int cmd, unsigned long arg );
@@ -158,9 +147,17 @@ extern void radeon_freelist_reset( drm_device_t *dev );
 extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
 
 extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
-extern void radeon_update_ring_snapshot( drm_radeon_private_t *dev_priv );
+
+static inline void
+radeon_update_ring_snapshot( drm_radeon_ring_buffer_t *ring )
+{
+	ring->space = (*(volatile int *)ring->head - ring->tail) * sizeof(u32);
+	if ( ring->space <= 0 )
+		ring->space += ring->size;
+}
 
 extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
+extern int radeon_do_cleanup_cp( drm_device_t *dev );
 extern int radeon_do_cleanup_pageflip( drm_device_t *dev );
 
 				/* radeon_state.c */
@@ -172,38 +169,13 @@ extern int radeon_cp_vertex( struct inode *inode, struct file *filp,
 			     unsigned int cmd, unsigned long arg );
 extern int radeon_cp_indices( struct inode *inode, struct file *filp,
 			      unsigned int cmd, unsigned long arg );
-extern int radeon_cp_blit( struct inode *inode, struct file *filp,
-			   unsigned int cmd, unsigned long arg );
+extern int radeon_cp_texture( struct inode *inode, struct file *filp,
+			      unsigned int cmd, unsigned long arg );
 extern int radeon_cp_stipple( struct inode *inode, struct file *filp,
 			      unsigned int cmd, unsigned long arg );
 extern int radeon_cp_indirect( struct inode *inode, struct file *filp,
 			       unsigned int cmd, unsigned long arg );
 
-				/* radeon_bufs.c */
-extern int radeon_addbufs(struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg);
-extern int radeon_mapbufs(struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg);
-
-				/* radeon_context.c */
-extern int  radeon_resctx(struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg);
-extern int  radeon_addctx(struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg);
-extern int  radeon_modctx(struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg);
-extern int  radeon_getctx(struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg);
-extern int  radeon_switchctx(struct inode *inode, struct file *filp,
-			     unsigned int cmd, unsigned long arg);
-extern int  radeon_newctx(struct inode *inode, struct file *filp,
-			  unsigned int cmd, unsigned long arg);
-extern int  radeon_rmctx(struct inode *inode, struct file *filp,
-			 unsigned int cmd, unsigned long arg);
-
-extern int  radeon_context_switch(drm_device_t *dev, int old, int new);
-extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
-
 
 /* Register definitions, register access macros and drmAddMap constants
  * for Radeon kernel driver.
@@ -462,6 +434,12 @@ extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
 
 #define RADEON_AIC_CNTL			0x01d0
 #	define RADEON_PCIGART_TRANSLATE_EN	(1 << 0)
+#define RADEON_AIC_STAT			0x01d4
+#define RADEON_AIC_PT_BASE		0x01d8
+#define RADEON_AIC_LO_ADDR		0x01dc
+#define RADEON_AIC_HI_ADDR		0x01e0
+#define RADEON_AIC_TLB_ADDR		0x01e4
+#define RADEON_AIC_TLB_DATA		0x01e8
 
 /* CP command packets */
 #define RADEON_CP_PACKET0		0x00000000
@@ -514,14 +492,14 @@ extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
 #define RADEON_COLOR_FORMAT_RGB8	9
 #define RADEON_COLOR_FORMAT_ARGB4444	15
 
-#define RADEON_TXF_8BPP_I		0
-#define RADEON_TXF_16BPP_AI88		1
-#define RADEON_TXF_8BPP_RGB332		2
-#define RADEON_TXF_16BPP_ARGB1555	3
-#define RADEON_TXF_16BPP_RGB565		4
-#define RADEON_TXF_16BPP_ARGB4444	5
-#define RADEON_TXF_32BPP_ARGB8888	6
-#define RADEON_TXF_32BPP_RGBA8888	7
+#define RADEON_TXFORMAT_I8		0
+#define RADEON_TXFORMAT_AI88		1
+#define RADEON_TXFORMAT_RGB332		2
+#define RADEON_TXFORMAT_ARGB1555	3
+#define RADEON_TXFORMAT_RGB565		4
+#define RADEON_TXFORMAT_ARGB4444	5
+#define RADEON_TXFORMAT_ARGB8888	6
+#define RADEON_TXFORMAT_RGBA8888	7
 
 /* Constants */
 #define RADEON_MAX_USEC_TIMEOUT		100000	/* 100 ms */
@@ -534,27 +512,51 @@ extern int  radeon_context_switch_complete(drm_device_t *dev, int new);
 #define RADEON_MAX_VB_AGE		0x7fffffff
 #define RADEON_MAX_VB_VERTS		(0xffff)
 
+#define RADEON_RING_HIGH_MARK		128
 
-#define RADEON_BASE(reg)	((u32)(dev_priv->mmio->handle))
-#define RADEON_ADDR(reg)	(RADEON_BASE(reg) + reg)
 
-#define RADEON_DEREF(reg)	*(__volatile__ u32 *)RADEON_ADDR(reg)
-#define RADEON_READ(reg)	RADEON_DEREF(reg)
-#define RADEON_WRITE(reg,val)	do { RADEON_DEREF(reg) = val; } while (0)
+#define RADEON_BASE(reg)	((unsigned long)(dev_priv->mmio->handle))
+#define RADEON_ADDR(reg)	(RADEON_BASE( reg ) + reg)
 
-#define RADEON_DEREF8(reg)	*(__volatile__ u8 *)RADEON_ADDR(reg)
-#define RADEON_READ8(reg)	RADEON_DEREF8(reg)
-#define RADEON_WRITE8(reg,val)	do { RADEON_DEREF8(reg) = val; } while (0)
+#define RADEON_DEREF(reg)	*(volatile u32 *)RADEON_ADDR( reg )
+#ifdef __alpha__
+#define RADEON_READ(reg)	(_RADEON_READ((u32 *)RADEON_ADDR( reg )))
+static inline u32 _RADEON_READ(u32 *addr) {
+	mb();
+	return *(volatile u32 *)addr;
+}
+#define RADEON_WRITE(reg,val) do {					\
+	wmb();
+	RADEON_DEREF(reg) = val;
+} while (0)
+#else
+#define RADEON_READ(reg)	RADEON_DEREF( reg )
+#define RADEON_WRITE(reg, val)	do { RADEON_DEREF( reg ) = val; } while (0)
+#endif
 
-#define RADEON_WRITE_PLL(addr,val)                                            \
-do {                                                                          \
-	RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX,                                \
-		      ((addr) & 0x1f) | RADEON_PLL_WR_EN);                    \
-	RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val));                          \
+#define RADEON_DEREF8(reg)	*(volatile u8 *)RADEON_ADDR( reg )
+#ifdef __alpha__
+#define RADEON_READ8(reg)	_RADEON_READ8((u8 *)RADEON_ADDR( reg ))
+static inline u8 _RADEON_READ8(u8 *addr) {
+	mb();
+	return *(volatile u8 *)addr;
+}
+#define RADEON_WRITE8(reg,val) do {					\
+	wmb();
+	RADEON_DEREF8( reg ) = val;
 } while (0)
+#else
+#define RADEON_READ8(reg)	RADEON_DEREF8( reg )
+#define RADEON_WRITE8(reg, val)	do { RADEON_DEREF8( reg ) = val; } while (0)
+#endif
 
-extern int RADEON_READ_PLL(drm_device_t *dev, int addr);
+#define RADEON_WRITE_PLL( addr, val ) do {				\
+	RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX,				\
+		       ((addr) & 0x1f) | RADEON_PLL_WR_EN );		\
+	RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) );			\
+} while (0)
 
+extern int RADEON_READ_PLL( drm_device_t *dev, int addr );
 
 
 #define CP_PACKET0( reg, n )						\
@@ -573,54 +575,46 @@ extern int RADEON_READ_PLL(drm_device_t *dev, int addr);
  * Engine control helper macros
  */
 
-#define RADEON_WAIT_UNTIL_2D_IDLE()					\
-do {									\
+#define RADEON_WAIT_UNTIL_2D_IDLE() do {				\
 	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
 	OUT_RING( (RADEON_WAIT_2D_IDLECLEAN |				\
 		   RADEON_WAIT_HOST_IDLECLEAN) );			\
 } while (0)
 
-#define RADEON_WAIT_UNTIL_3D_IDLE()					\
-do {									\
+#define RADEON_WAIT_UNTIL_3D_IDLE() do {				\
 	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
 	OUT_RING( (RADEON_WAIT_3D_IDLECLEAN |				\
 		   RADEON_WAIT_HOST_IDLECLEAN) );			\
 } while (0)
 
-#define RADEON_WAIT_UNTIL_IDLE()					\
-do {									\
+#define RADEON_WAIT_UNTIL_IDLE() do {					\
 	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
 	OUT_RING( (RADEON_WAIT_2D_IDLECLEAN |				\
 		   RADEON_WAIT_3D_IDLECLEAN |				\
 		   RADEON_WAIT_HOST_IDLECLEAN) );			\
 } while (0)
 
-#define RADEON_WAIT_UNTIL_PAGE_FLIPPED()				\
-do {									\
+#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do {				\
 	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
 	OUT_RING( RADEON_WAIT_CRTC_PFLIP );				\
 } while (0)
 
-#define RADEON_FLUSH_CACHE()						\
-do {									\
+#define RADEON_FLUSH_CACHE() do {					\
 	OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) );	\
 	OUT_RING( RADEON_RB2D_DC_FLUSH );				\
 } while (0)
 
-#define RADEON_PURGE_CACHE()						\
-do {									\
+#define RADEON_PURGE_CACHE() do {					\
 	OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) );	\
 	OUT_RING( RADEON_RB2D_DC_FLUSH_ALL );				\
 } while (0)
 
-#define RADEON_FLUSH_ZCACHE()						\
-do {									\
+#define RADEON_FLUSH_ZCACHE() do {					\
 	OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );	\
 	OUT_RING( RADEON_RB3D_ZC_FLUSH );				\
 } while (0)
 
-#define RADEON_PURGE_ZCACHE()						\
-do {									\
+#define RADEON_PURGE_ZCACHE() do {					\
 	OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );	\
 	OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL );				\
 } while (0)
@@ -630,7 +624,33 @@ do {									\
  * Misc helper macros
  */
 
-#define VB_AGE_CHECK_WITH_RET( dev_priv )				\
+#define LOCK_TEST_WITH_RETURN( dev )					\
+do {									\
+	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||		\
+	     dev->lock.pid != current->pid ) {				\
+		DRM_ERROR( "%s called without lock held\n",		\
+			   __FUNCTION__ );				\
+		return -EINVAL;						\
+	}								\
+} while (0)
+
+#define RING_SPACE_TEST_WITH_RETURN( dev_priv )				\
+do {									\
+	drm_radeon_ring_buffer_t *ring = &dev_priv->ring; int i;	\
+	if ( ring->space < ring->high_mark ) {				\
+		for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {	\
+			radeon_update_ring_snapshot( ring );		\
+			if ( ring->space >= ring->high_mark )		\
+				goto __ring_space_done;			\
+			udelay( 1 );					\
+		}							\
+		DRM_ERROR( "ring space check failed!\n" );		\
+		return -EBUSY;						\
+	}								\
+ __ring_space_done:							\
+} while (0)
+
+#define VB_AGE_TEST_WITH_RETURN( dev_priv )				\
 do {									\
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;		\
 	if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) {		\
@@ -641,20 +661,17 @@ do {									\
 	}								\
 } while (0)
 
-#define RADEON_DISPATCH_AGE( age )					\
-do {									\
+#define RADEON_DISPATCH_AGE( age ) do {					\
 	OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) );		\
 	OUT_RING( age );						\
 } while (0)
 
-#define RADEON_FRAME_AGE( age )						\
-do {									\
+#define RADEON_FRAME_AGE( age ) do {					\
 	OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) );		\
 	OUT_RING( age );						\
 } while (0)
 
-#define RADEON_CLEAR_AGE( age )						\
-do {									\
+#define RADEON_CLEAR_AGE( age ) do {					\
 	OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) );		\
 	OUT_RING( age );						\
 } while (0)
@@ -676,7 +693,7 @@ do {									\
 		DRM_INFO( "BEGIN_RING( %d ) in %s\n",			\
 			   n, __FUNCTION__ );				\
 	}								\
-	if ( dev_priv->ring.space < (n) * sizeof(u32) ) {		\
+	if ( dev_priv->ring.space <= (n) * sizeof(u32) ) {		\
 		radeon_wait_ring( dev_priv, (n) * sizeof(u32) );	\
 	}								\
 	dev_priv->ring.space -= (n) * sizeof(u32);			\
@@ -687,7 +704,7 @@ do {									\
 
 #define ADVANCE_RING() do {						\
 	if ( RADEON_VERBOSE ) {						\
-		DRM_INFO( "ADVANCE_RING() tail=0x%06x wr=0x%06x\n",	\
+		DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n",	\
 			  write, dev_priv->ring.tail );			\
 	}								\
 	radeon_flush_write_combine();					\