renesas/drm.git - libdrm, cloned from git://anongit.freedesktop.org/mesa/drm

diff options

author	Alex Deucher <alex@cube.(none)>	2008-05-13 21:02:17 -0400
committer	Alex Deucher <alex@cube.(none)>	2008-05-13 21:02:17 -0400
commit	caace3692f3121dcc18fa5e9260ffe1a4abbb943 (patch)
tree	13a897e0ffc66e80d52bd3885edaec3ce31e9900 /linux-core
parent	10d754f0a2ba2bdda87c243305c8fc46616e965c (diff)

RS4xx: separate out RS400 and RS480 IGP chips

RS400 (intel based IGP) and RS480 (AMD based IGP) have different MC and GART setups. Currently we only support RS480.

Diffstat (limited to 'linux-core')

0 files changed, 0 insertions, 0 deletions

n95' href='#n95'>95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651

/*
 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sub license,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#ifndef VIA_3D_REG_H
#define VIA_3D_REG_H
#define HC_REG_BASE             0x0400

#define HC_REG_TRANS_SPACE      0x0040

#define HC_ParaN_MASK           0xffffffff
#define HC_Para_MASK            0x00ffffff
#define HC_SubA_MASK            0xff000000
#define HC_SubA_SHIFT           24
/* Transmission Setting
 */
#define HC_REG_TRANS_SET        0x003c
#define HC_ParaSubType_MASK     0xff000000
#define HC_ParaType_MASK        0x00ff0000
#define HC_ParaOS_MASK          0x0000ff00
#define HC_ParaAdr_MASK         0x000000ff
#define HC_ParaSubType_SHIFT    24
#define HC_ParaType_SHIFT       16
#define HC_ParaOS_SHIFT         8
#define HC_ParaAdr_SHIFT        0

#define HC_ParaType_CmdVdata    0x0000
#define HC_ParaType_NotTex      0x0001
#define HC_ParaType_Tex         0x0002
#define HC_ParaType_Palette     0x0003
#define HC_ParaType_PreCR       0x0010
#define HC_ParaType_Auto        0x00fe

/* Transmission Space
 */
#define HC_REG_Hpara0           0x0040
#define HC_REG_HpataAF          0x02fc

/* Read
 */
#define HC_REG_HREngSt          0x0000
#define HC_REG_HRFIFOempty      0x0004
#define HC_REG_HRFIFOfull       0x0008
#define HC_REG_HRErr            0x000c
#define HC_REG_FIFOstatus       0x0010
/* HC_REG_HREngSt          0x0000
 */
#define HC_HDASZC_MASK          0x00010000
#define HC_HSGEMI_MASK          0x0000f000
#define HC_HLGEMISt_MASK        0x00000f00
#define HC_HCRSt_MASK           0x00000080
#define HC_HSE0St_MASK          0x00000040
#define HC_HSE1St_MASK          0x00000020
#define HC_HPESt_MASK           0x00000010
#define HC_HXESt_MASK           0x00000008
#define HC_HBESt_MASK           0x00000004
#define HC_HE2St_MASK           0x00000002
#define HC_HE3St_MASK           0x00000001
/* HC_REG_HRFIFOempty      0x0004
 */
#define HC_HRZDempty_MASK       0x00000010
#define HC_HRTXAempty_MASK      0x00000008
#define HC_HRTXDempty_MASK      0x00000004
#define HC_HWZDempty_MASK       0x00000002
#define HC_HWCDempty_MASK       0x00000001
/* HC_REG_HRFIFOfull       0x0008
 */
#define HC_HRZDfull_MASK        0x00000010
#define HC_HRTXAfull_MASK       0x00000008
#define HC_HRTXDfull_MASK       0x00000004
#define HC_HWZDfull_MASK        0x00000002
#define HC_HWCDfull_MASK        0x00000001
/* HC_REG_HRErr            0x000c
 */
#define HC_HAGPCMErr_MASK       0x80000000
#define HC_HAGPCMErrC_MASK      0x70000000
/* HC_REG_FIFOstatus       0x0010
 */
#define HC_HRFIFOATall_MASK     0x80000000
#define HC_HRFIFOATbusy_MASK    0x40000000
#define HC_HRATFGMDo_MASK       0x00000100
#define HC_HRATFGMDi_MASK       0x00000080
#define HC_HRATFRZD_MASK        0x00000040
#define HC_HRATFRTXA_MASK       0x00000020
#define HC_HRATFRTXD_MASK       0x00000010
#define HC_HRATFWZD_MASK        0x00000008
#define HC_HRATFWCD_MASK        0x00000004
#define HC_HRATTXTAG_MASK       0x00000002
#define HC_HRATTXCH_MASK        0x00000001

/* AGP Command Setting
 */
#define HC_SubA_HAGPBstL        0x0060
#define HC_SubA_HAGPBendL       0x0061
#define HC_SubA_HAGPCMNT        0x0062
#define HC_SubA_HAGPBpL         0x0063
#define HC_SubA_HAGPBpH         0x0064
/* HC_SubA_HAGPCMNT        0x0062
 */
#define HC_HAGPCMNT_MASK        0x00800000
#define HC_HCmdErrClr_MASK      0x00400000
#define HC_HAGPBendH_MASK       0x0000ff00
#define HC_HAGPBstH_MASK        0x000000ff
#define HC_HAGPBendH_SHIFT      8
#define HC_HAGPBstH_SHIFT       0
/* HC_SubA_HAGPBpL         0x0063
 */
#define HC_HAGPBpL_MASK         0x00fffffc
#define HC_HAGPBpID_MASK        0x00000003
#define HC_HAGPBpID_PAUSE       0x00000000
#define HC_HAGPBpID_JUMP        0x00000001
#define HC_HAGPBpID_STOP        0x00000002
/* HC_SubA_HAGPBpH         0x0064
 */
#define HC_HAGPBpH_MASK         0x00ffffff

/* Miscellaneous Settings
 */
#define HC_SubA_HClipTB         0x0070
#define HC_SubA_HClipLR         0x0071
#define HC_SubA_HFPClipTL       0x0072
#define HC_SubA_HFPClipBL       0x0073
#define HC_SubA_HFPClipLL       0x0074
#define HC_SubA_HFPClipRL       0x0075
#define HC_SubA_HFPClipTBH      0x0076
#define HC_SubA_HFPClipLRH      0x0077
#define HC_SubA_HLP             0x0078
#define HC_SubA_HLPRF           0x0079
#define HC_SubA_HSolidCL        0x007a
#define HC_SubA_HPixGC          0x007b
#define HC_SubA_HSPXYOS         0x007c
#define HC_SubA_HVertexCNT      0x007d

#define HC_HClipT_MASK          0x00fff000
#define HC_HClipT_SHIFT         12
#define HC_HClipB_MASK          0x00000fff
#define HC_HClipB_SHIFT         0
#define HC_HClipL_MASK          0x00fff000
#define HC_HClipL_SHIFT         12
#define HC_HClipR_MASK          0x00000fff
#define HC_HClipR_SHIFT         0
#define HC_HFPClipBH_MASK       0x0000ff00
#define HC_HFPClipBH_SHIFT      8
#define HC_HFPClipTH_MASK       0x000000ff
#define HC_HFPClipTH_SHIFT      0
#define HC_HFPClipRH_MASK       0x0000ff00
#define HC_HFPClipRH_SHIFT      8
#define HC_HFPClipLH_MASK       0x000000ff
#define HC_HFPClipLH_SHIFT      0
#define HC_HSolidCH_MASK        0x000000ff
#define HC_HPixGC_MASK          0x00800000
#define HC_HSPXOS_MASK          0x00fff000
#define HC_HSPXOS_SHIFT         12
#define HC_HSPYOS_MASK          0x00000fff

/* Command
 * Command A
 */
#define HC_HCmdHeader_MASK      0xfe000000	/*0xffe00000 */
#define HC_HE3Fire_MASK         0x00100000
#define HC_HPMType_MASK         0x000f0000
#define HC_HEFlag_MASK          0x0000e000
#define HC_HShading_MASK        0x00001c00
#define HC_HPMValidN_MASK       0x00000200
#define HC_HPLEND_MASK          0x00000100
#define HC_HVCycle_MASK         0x000000ff
#define HC_HVCycle_Style_MASK   0x000000c0
#define HC_HVCycle_ChgA_MASK    0x00000030
#define HC_HVCycle_ChgB_MASK    0x0000000c
#define HC_HVCycle_ChgC_MASK    0x00000003
#define HC_HPMType_Point        0x00000000
#define HC_HPMType_Line         0x00010000
#define HC_HPMType_Tri          0x00020000
#define HC_HPMType_TriWF        0x00040000
#define HC_HEFlag_NoAA          0x00000000
#define HC_HEFlag_ab            0x00008000
#define HC_HEFlag_bc            0x00004000
#define HC_HEFlag_ca            0x00002000
#define HC_HShading_Solid       0x00000000
#define HC_HShading_FlatA       0x00000400
#define HC_HShading_FlatB       0x00000800
#define HC_HShading_FlatC       0x00000c00
#define HC_HShading_Gouraud     0x00001000
#define HC_HVCycle_Full         0x00000000
#define HC_HVCycle_AFP          0x00000040
#define HC_HVCycle_One          0x000000c0
#define HC_HVCycle_NewA         0x00000000
#define HC_HVCycle_AA           0x00000010
#define HC_HVCycle_AB           0x00000020
#define HC_HVCycle_AC           0x00000030
#define HC_HVCycle_NewB         0x00000000
#define HC_HVCycle_BA           0x00000004
#define HC_HVCycle_BB           0x00000008
#define HC_HVCycle_BC           0x0000000c
#define HC_HVCycle_NewC         0x00000000
#define HC_HVCycle_CA           0x00000001
#define HC_HVCycle_CB           0x00000002
#define HC_HVCycle_CC           0x00000003

/* Command B
 */
#define HC_HLPrst_MASK          0x00010000
#define HC_HLLastP_MASK         0x00008000
#define HC_HVPMSK_MASK          0x00007f80
#define HC_HBFace_MASK          0x00000040
#define HC_H2nd1VT_MASK         0x0000003f
#define HC_HVPMSK_X             0x00004000
#define HC_HVPMSK_Y             0x00002000
#define HC_HVPMSK_Z             0x00001000
#define HC_HVPMSK_W             0x00000800
#define HC_HVPMSK_Cd            0x00000400
#define HC_HVPMSK_Cs            0x00000200
#define HC_HVPMSK_S             0x00000100
#define HC_HVPMSK_T             0x00000080

/* Enable Setting
 */
#define HC_SubA_HEnable         0x0000
#define HC_HenTXEnvMap_MASK     0x00200000
#define HC_HenVertexCNT_MASK    0x00100000
#define HC_HenCPUDAZ_MASK       0x00080000
#define HC_HenDASZWC_MASK       0x00040000
#define HC_HenFBCull_MASK       0x00020000
#define HC_HenCW_MASK           0x00010000
#define HC_HenAA_MASK           0x00008000
#define HC_HenST_MASK           0x00004000
#define HC_HenZT_MASK           0x00002000
#define HC_HenZW_MASK           0x00001000
#define HC_HenAT_MASK           0x00000800
#define HC_HenAW_MASK           0x00000400
#define HC_HenSP_MASK           0x00000200
#define HC_HenLP_MASK           0x00000100
#define HC_HenTXCH_MASK         0x00000080
#define HC_HenTXMP_MASK         0x00000040
#define HC_HenTXPP_MASK         0x00000020
#define HC_HenTXTR_MASK         0x00000010
#define HC_HenCS_MASK           0x00000008
#define HC_HenFOG_MASK          0x00000004
#define HC_HenABL_MASK          0x00000002
#define HC_HenDT_MASK           0x00000001

/* Z Setting
 */
#define HC_SubA_HZWBBasL        0x0010
#define HC_SubA_HZWBBasH        0x0011
#define HC_SubA_HZWBType        0x0012
#define HC_SubA_HZBiasL         0x0013
#define HC_SubA_HZWBend         0x0014
#define HC_SubA_HZWTMD          0x0015
#define HC_SubA_HZWCDL          0x0016
#define HC_SubA_HZWCTAGnum      0x0017
#define HC_SubA_HZCYNum         0x0018
#define HC_SubA_HZWCFire        0x0019
/* HC_SubA_HZWBType
 */
#define HC_HZWBType_MASK        0x00800000
#define HC_HZBiasedWB_MASK      0x00400000
#define HC_HZONEasFF_MASK       0x00200000
#define HC_HZOONEasFF_MASK      0x00100000
#define HC_HZWBFM_MASK          0x00030000
#define HC_HZWBLoc_MASK         0x0000c000
#define HC_HZWBPit_MASK         0x00003fff
#define HC_HZWBFM_16            0x00000000
#define HC_HZWBFM_32            0x00020000
#define HC_HZWBFM_24            0x00030000
#define HC_HZWBLoc_Local        0x00000000
#define HC_HZWBLoc_SyS          0x00004000
/* HC_SubA_HZWBend
 */
#define HC_HZWBend_MASK         0x00ffe000
#define HC_HZBiasH_MASK         0x000000ff
#define HC_HZWBend_SHIFT        10
/* HC_SubA_HZWTMD
 */
#define HC_HZWTMD_MASK          0x00070000
#define HC_HEBEBias_MASK        0x00007f00
#define HC_HZNF_MASK            0x000000ff
#define HC_HZWTMD_NeverPass     0x00000000
#define HC_HZWTMD_LT            0x00010000
#define HC_HZWTMD_EQ            0x00020000
#define HC_HZWTMD_LE            0x00030000
#define HC_HZWTMD_GT            0x00040000
#define HC_HZWTMD_NE            0x00050000
#define HC_HZWTMD_GE            0x00060000
#define HC_HZWTMD_AllPass       0x00070000
#define HC_HEBEBias_SHIFT       8
/* HC_SubA_HZWCDL          0x0016
 */
#define HC_HZWCDL_MASK          0x00ffffff
/* HC_SubA_HZWCTAGnum      0x0017
 */
#define HC_HZWCTAGnum_MASK      0x00ff0000
#define HC_HZWCTAGnum_SHIFT     16
#define HC_HZWCDH_MASK          0x000000ff
#define HC_HZWCDH_SHIFT         0
/* HC_SubA_HZCYNum         0x0018
 */
#define HC_HZCYNum_MASK         0x00030000
#define HC_HZCYNum_SHIFT        16
#define HC_HZWCQWnum_MASK       0x00003fff
#define HC_HZWCQWnum_SHIFT      0
/* HC_SubA_HZWCFire        0x0019
 */
#define HC_ZWCFire_MASK         0x00010000
#define HC_HZWCQWnumLast_MASK   0x00003fff
#define HC_HZWCQWnumLast_SHIFT  0

/* Stencil Setting
 */
#define HC_SubA_HSTREF          0x0023
#define HC_SubA_HSTMD           0x0024
/* HC_SubA_HSBFM
 */
#define HC_HSBFM_MASK           0x00030000
#define HC_HSBLoc_MASK          0x0000c000
#define HC_HSBPit_MASK          0x00003fff
/* HC_SubA_HSTREF
 */
#define HC_HSTREF_MASK          0x00ff0000
#define HC_HSTOPMSK_MASK        0x0000ff00
#define HC_HSTBMSK_MASK         0x000000ff
#define HC_HSTREF_SHIFT         16
#define HC_HSTOPMSK_SHIFT       8
/* HC_SubA_HSTMD
 */
#define HC_HSTMD_MASK           0x00070000
#define HC_HSTOPSF_MASK         0x000001c0
#define HC_HSTOPSPZF_MASK       0x00000038
#define HC_HSTOPSPZP_MASK       0x00000007
#define HC_HSTMD_NeverPass      0x00000000
#define HC_HSTMD_LT             0x00010000
#define HC_HSTMD_EQ             0x00020000
#define HC_HSTMD_LE             0x00030000
#define HC_HSTMD_GT             0x00040000
#define HC_HSTMD_NE             0x00050000
#define HC_HSTMD_GE             0x00060000
#define HC_HSTMD_AllPass        0x00070000
#define HC_HSTOPSF_KEEP         0x00000000
#define HC_HSTOPSF_ZERO         0x00000040
#define HC_HSTOPSF_REPLACE      0x00000080
#define HC_HSTOPSF_INCRSAT      0x000000c0
#define HC_HSTOPSF_DECRSAT      0x00000100
#define HC_HSTOPSF_INVERT       0x00000140
#define HC_HSTOPSF_INCR         0x00000180
#define HC_HSTOPSF_DECR         0x000001c0
#define HC_HSTOPSPZF_KEEP       0x00000000
#define HC_HSTOPSPZF_ZERO       0x00000008
#define HC_HSTOPSPZF_REPLACE    0x00000010
#define HC_HSTOPSPZF_INCRSAT    0x00000018
#define HC_HSTOPSPZF_DECRSAT    0x00000020
#define HC_HSTOPSPZF_INVERT     0x00000028
#define HC_HSTOPSPZF_INCR       0x00000030
#define HC_HSTOPSPZF_DECR       0x00000038
#define HC_HSTOPSPZP_KEEP       0x00000000
#define HC_HSTOPSPZP_ZERO       0x00000001
#define HC_HSTOPSPZP_REPLACE    0x00000002
#define HC_HSTOPSPZP_INCRSAT    0x00000003
#define HC_HSTOPSPZP_DECRSAT    0x00000004
#define HC_HSTOPSPZP_INVERT     0x00000005
#define HC_HSTOPSPZP_INCR       0x00000006
#define HC_HSTOPSPZP_DECR       0x00000007

/* Alpha Setting
 */
#define HC_SubA_HABBasL         0x0030
#define HC_SubA_HABBasH         0x0031
#define HC_SubA_HABFM           0x0032
#define HC_SubA_HATMD           0x0033
#define HC_SubA_HABLCsat        0x0034
#define HC_SubA_HABLCop         0x0035
#define HC_SubA_HABLAsat        0x0036
#define HC_SubA_HABLAop         0x0037
#define HC_SubA_HABLRCa         0x0038
#define HC_SubA_HABLRFCa        0x0039
#define HC_SubA_HABLRCbias      0x003a
#define HC_SubA_HABLRCb         0x003b
#define HC_SubA_HABLRFCb        0x003c
#define HC_SubA_HABLRAa         0x003d
#define HC_SubA_HABLRAb         0x003e
/* HC_SubA_HABFM
 */
#define HC_HABFM_MASK           0x00030000
#define HC_HABLoc_MASK          0x0000c000
#define HC_HABPit_MASK          0x000007ff
/* HC_SubA_HATMD
 */
#define HC_HATMD_MASK           0x00000700
#define HC_HATREF_MASK          0x000000ff
#define HC_HATMD_NeverPass      0x00000000
#define HC_HATMD_LT             0x00000100
#define HC_HATMD_EQ             0x00000200
#define HC_HATMD_LE             0x00000300
#define HC_HATMD_GT             0x00000400
#define HC_HATMD_NE             0x00000500
#define HC_HATMD_GE             0x00000600
#define HC_HATMD_AllPass        0x00000700
/* HC_SubA_HABLCsat
 */
#define HC_HABLCsat_MASK        0x00010000
#define HC_HABLCa_MASK          0x0000fc00
#define HC_HABLCa_C_MASK        0x0000c000
#define HC_HABLCa_OPC_MASK      0x00003c00
#define HC_HABLFCa_MASK         0x000003f0
#define HC_HABLFCa_C_MASK       0x00000300
#define HC_HABLFCa_OPC_MASK     0x000000f0
#define HC_HABLCbias_MASK       0x0000000f
#define HC_HABLCbias_C_MASK     0x00000008
#define HC_HABLCbias_OPC_MASK   0x00000007
/*-- Define the input color.
 */
#define HC_XC_Csrc              0x00000000
#define HC_XC_Cdst              0x00000001
#define HC_XC_Asrc              0x00000002
#define HC_XC_Adst              0x00000003
#define HC_XC_Fog               0x00000004
#define HC_XC_HABLRC            0x00000005
#define HC_XC_minSrcDst         0x00000006
#define HC_XC_maxSrcDst         0x00000007
#define HC_XC_mimAsrcInvAdst    0x00000008
#define HC_XC_OPC               0x00000000
#define HC_XC_InvOPC            0x00000010
#define HC_XC_OPCp5             0x00000020
/*-- Define the input Alpha
 */
#define HC_XA_OPA               0x00000000
#define HC_XA_InvOPA            0x00000010
#define HC_XA_OPAp5             0x00000020
#define HC_XA_0                 0x00000000
#define HC_XA_Asrc              0x00000001
#define HC_XA_Adst              0x00000002
#define HC_XA_Fog               0x00000003
#define HC_XA_minAsrcFog        0x00000004
#define HC_XA_minAsrcAdst       0x00000005
#define HC_XA_maxAsrcFog        0x00000006
#define HC_XA_maxAsrcAdst       0x00000007
#define HC_XA_HABLRA            0x00000008
#define HC_XA_minAsrcInvAdst    0x00000008
#define HC_XA_HABLFRA           0x00000009
/*--
 */
#define HC_HABLCa_OPC           (HC_XC_OPC << 10)
#define HC_HABLCa_InvOPC        (HC_XC_InvOPC << 10)
#define HC_HABLCa_OPCp5         (HC_XC_OPCp5 << 10)
#define HC_HABLCa_Csrc          (HC_XC_Csrc << 10)
#define HC_HABLCa_Cdst          (HC_XC_Cdst << 10)
#define HC_HABLCa_Asrc          (HC_XC_Asrc << 10)
#define HC_HABLCa_Adst          (HC_XC_Adst << 10)
#define HC_HABLCa_Fog           (HC_XC_Fog << 10)
#define HC_HABLCa_HABLRCa       (HC_XC_HABLRC << 10)
#define HC_HABLCa_minSrcDst     (HC_XC_minSrcDst << 10)
#define HC_HABLCa_maxSrcDst     (HC_XC_maxSrcDst << 10)
#define HC_HABLFCa_OPC              (HC_XC_OPC << 4)
#define HC_HABLFCa_InvOPC           (HC_XC_InvOPC << 4)
#define HC_HABLFCa_OPCp5            (HC_XC_OPCp5 << 4)
#define HC_HABLFCa_Csrc             (HC_XC_Csrc << 4)
#define HC_HABLFCa_Cdst             (HC_XC_Cdst << 4)
#define HC_HABLFCa_Asrc             (HC_XC_Asrc << 4)
#define HC_HABLFCa_Adst             (HC_XC_Adst << 4)
#define HC_HABLFCa_Fog              (HC_XC_Fog << 4)
#define HC_HABLFCa_HABLRCa          (HC_XC_HABLRC << 4)
#define HC_HABLFCa_minSrcDst        (HC_XC_minSrcDst << 4)
#define HC_HABLFCa_maxSrcDst        (HC_XC_maxSrcDst << 4)
#define HC_HABLFCa_mimAsrcInvAdst   (HC_XC_mimAsrcInvAdst << 4)
#define HC_HABLCbias_HABLRCbias 0x00000000
#define HC_HABLCbias_Asrc       0x00000001
#define HC_HABLCbias_Adst       0x00000002
#define HC_HABLCbias_Fog        0x00000003
#define HC_HABLCbias_Cin        0x00000004
/* HC_SubA_HABLCop         0x0035
 */
#define HC_HABLdot_MASK         0x00010000
#define HC_HABLCop_MASK         0x00004000
#define HC_HABLCb_MASK          0x00003f00
#define HC_HABLCb_C_MASK        0x00003000
#define HC_HABLCb_OPC_MASK      0x00000f00


context:
space:
mode: