diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2008-09-18 17:27:00 -0400 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2008-09-18 17:27:00 -0400 |
| commit | 075ed1d6fd1d58c1f46d556df79f44153f10edd8 (patch) | |
| tree | de4a63fd79a0a19a75d9bc07ef4aed9dd2ac7432 /linux-core/radeon_legacy_crtc.c | |
| parent | 6988176195450da9033a0f0f21eafc6ae0a7a6a4 (diff) | |
radeon: pll and interlace updates from the ddx
also some formatting cleanup in radeon_reg.h
Diffstat (limited to 'linux-core/radeon_legacy_crtc.c')
| -rw-r--r-- | linux-core/radeon_legacy_crtc.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/linux-core/radeon_legacy_crtc.c b/linux-core/radeon_legacy_crtc.c index f029c478..d51fc52d 100644 --- a/linux-core/radeon_legacy_crtc.c +++ b/linux-core/radeon_legacy_crtc.c @@ -401,7 +401,7 @@ static void radeon_set_pll1(struct drm_crtc *crtc, struct drm_display_mode *mode uint32_t post_divider = 0; uint32_t freq = 0; uint8_t pll_gain; - int pll_flags = RADEON_PLL_LEGACY | RADEON_PLL_PREFER_LOW_REF_DIV; + int pll_flags = RADEON_PLL_LEGACY; bool use_bios_divs = false; /* PLL registers */ uint32_t ppll_ref_div = 0; @@ -431,6 +431,11 @@ static void radeon_set_pll1(struct drm_crtc *crtc, struct drm_display_mode *mode { 0, 0 } }; + if (mode->clock > 120000) /* range limits??? */ + pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; + else + pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { if (encoder->crtc == crtc) { if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |