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authorJesse Barnes <jesse.barnes@intel.com>2007-11-01 15:27:55 -0700
committerJesse Barnes <jesse.barnes@intel.com>2007-11-01 15:27:55 -0700
commit629c8b0dbf975632473d848f60606baf309f2f3b (patch)
tree9b85064c2673527cb7515af7e356bb47aaa4639f /linux-core/i915_compat.c
parent90d8f792794d46d1a8e998856bc7bbe54596114b (diff)
parent5766d81074d6faa7f14b45635765cdb7209597fc (diff)
Merge branch 'master' into modesetting-101
Conflicts: linux-core/Makefile.kernel linux-core/drm_stub.c linux-core/i915_drv.c shared-core/i915_dma.c shared-core/i915_drv.h Fixup suspend/resume conflicts (basically use what's in DRM master for now). Also fix up a few other conflicts that snuck in (i915_dma changes etc.).
Diffstat (limited to 'linux-core/i915_compat.c')
-rw-r--r--linux-core/i915_compat.c140
1 files changed, 140 insertions, 0 deletions
diff --git a/linux-core/i915_compat.c b/linux-core/i915_compat.c
new file mode 100644
index 00000000..969d5977
--- /dev/null
+++ b/linux-core/i915_compat.c
@@ -0,0 +1,140 @@
+#include "drmP.h"
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
+
+#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
+#define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980
+#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
+#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
+#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
+#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
+#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
+#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
+#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
+#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
+
+#define IS_I965 (agp_dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
+ agp_dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
+ agp_dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
+ agp_dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
+ agp_dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
+ agp_dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
+
+#define IS_G33 (agp_dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
+ agp_dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
+ agp_dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
+
+#define I915_IFPADDR 0x60
+#define I965_IFPADDR 0x70
+
+static struct _intel_private_compat {
+ void __iomem *flush_page;
+ struct resource ifp_resource;
+} intel_private;
+
+static void
+intel_compat_align_resource(void *data, struct resource *res,
+ resource_size_t size, resource_size_t align)
+{
+ return;
+}
+
+
+static int intel_alloc_chipset_flush_resource(struct pci_dev *pdev)
+{
+ int ret;
+ ret = pci_bus_alloc_resource(pdev->bus, &intel_private.ifp_resource, PAGE_SIZE,
+ PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
+ intel_compat_align_resource, pdev);
+ if (ret != 0)
+ return ret;
+
+ return 0;
+}
+
+static void intel_i915_setup_chipset_flush(struct pci_dev *pdev)
+{
+ int ret;
+ u32 temp;
+
+ pci_read_config_dword(pdev, I915_IFPADDR, &temp);
+ if (!(temp & 0x1)) {
+ intel_alloc_chipset_flush_resource(pdev);
+
+ pci_write_config_dword(pdev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
+ } else {
+ temp &= ~1;
+
+ intel_private.ifp_resource.start = temp;
+ intel_private.ifp_resource.end = temp + PAGE_SIZE;
+ ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
+ if (ret) {
+ intel_private.ifp_resource.start = 0;
+ printk("Failed inserting resource into tree\n");
+ }
+ }
+}
+
+static void intel_i965_g33_setup_chipset_flush(struct pci_dev *pdev)
+{
+ u32 temp_hi, temp_lo;
+ int ret;
+
+ pci_read_config_dword(pdev, I965_IFPADDR + 4, &temp_hi);
+ pci_read_config_dword(pdev, I965_IFPADDR, &temp_lo);
+
+ if (!(temp_lo & 0x1)) {
+
+ intel_alloc_chipset_flush_resource(pdev);
+
+ pci_write_config_dword(pdev, I965_IFPADDR + 4, (intel_private.ifp_resource.start >> 32));
+ pci_write_config_dword(pdev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
+ } else {
+ u64 l64;
+
+ temp_lo &= ~0x1;
+ l64 = ((u64)temp_hi << 32) | temp_lo;
+
+ intel_private.ifp_resource.start = l64;
+ intel_private.ifp_resource.end = l64 + PAGE_SIZE;
+ ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
+ if (!ret) {
+ intel_private.ifp_resource.start = 0;
+ printk("Failed inserting resource into tree\n");
+ }
+ }
+}
+
+void intel_init_chipset_flush_compat(struct drm_device *dev)
+{
+ struct pci_dev *agp_dev = dev->agp->agp_info.device;
+
+ intel_private.ifp_resource.name = "GMCH IFPBAR";
+ intel_private.ifp_resource.flags = IORESOURCE_MEM;
+
+ /* Setup chipset flush for 915 */
+ if (IS_I965 || IS_G33) {
+ intel_i965_g33_setup_chipset_flush(agp_dev);
+ } else {
+ intel_i915_setup_chipset_flush(agp_dev);
+ }
+
+ if (intel_private.ifp_resource.start) {
+ intel_private.flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
+ if (!intel_private.flush_page)
+ printk("unable to ioremap flush page - no chipset flushing");
+ }
+}
+
+void intel_fini_chipset_flush_compat(struct drm_device *dev)
+{
+ iounmap(intel_private.flush_page);
+ release_resource(&intel_private.ifp_resource);
+}
+
+void drm_agp_chipset_flush(struct drm_device *dev)
+{
+ if (intel_private.flush_page)
+ writel(1, intel_private.flush_page);
+}
+#endif