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authorEric Anholt <eric@anholt.net>2008-11-13 11:44:22 -0800
committerEric Anholt <eric@anholt.net>2008-12-02 12:19:34 -0800
commit6fb1ad767d64acbd904865bb429547c3805839cf (patch)
tree51831b727fd941d392386cdc2f3baa322d57c3ad /libdrm
parent7e4e0fbbb82b0467d46386bcac1115812aaa1393 (diff)
intel: Add a function for setting (GTT,GTT) domain, for use by UXA.
This function can also serve the role that the bo_wait_rendering did, when write_enable is unset.
Diffstat (limited to 'libdrm')
-rw-r--r--libdrm/intel/intel_bufmgr.h1
-rw-r--r--libdrm/intel/intel_bufmgr_gem.c16
2 files changed, 16 insertions, 1 deletions
diff --git a/libdrm/intel/intel_bufmgr.h b/libdrm/intel/intel_bufmgr.h
index 361e4345..f134f169 100644
--- a/libdrm/intel/intel_bufmgr.h
+++ b/libdrm/intel/intel_bufmgr.h
@@ -106,6 +106,7 @@ drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
unsigned int handle);
void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
+void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
/* drm_intel_bufmgr_fake.c */
drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd,
diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c
index be41474b..e681eee7 100644
--- a/libdrm/intel/intel_bufmgr_gem.c
+++ b/libdrm/intel/intel_bufmgr_gem.c
@@ -729,9 +729,23 @@ drm_intel_gem_bo_get_subdata (drm_intel_bo *bo, unsigned long offset,
return 0;
}
+/** Waits for all GPU rendering to the object to have completed. */
static void
drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
{
+ return drm_intel_gem_bo_start_gtt_access(bo, 0);
+}
+
+/**
+ * Sets the object to the GTT read and possibly write domain, used by the X
+ * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
+ *
+ * In combination with drm_intel_gem_bo_pin() and manual fence management, we
+ * can do tiled pixmaps this way.
+ */
+void
+drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
+{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
struct drm_i915_gem_set_domain set_domain;
@@ -739,7 +753,7 @@ drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
set_domain.handle = bo_gem->gem_handle;
set_domain.read_domains = I915_GEM_DOMAIN_GTT;
- set_domain.write_domain = 0;
+ set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
do {
ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
} while (ret == -1 && errno == EINTR);