diff options
author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2008-12-03 11:54:07 -0800 |
---|---|---|
committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2008-12-03 11:54:07 -0800 |
commit | 12e68f8059485fb4f02a15f74ab2fa3bdff38c81 (patch) | |
tree | 3970daf68cc737d0ec4a53614cd92e7e2a518455 /libdrm/intel | |
parent | d5d5aca7f959f0e357f99dd517a421c015d0712f (diff) | |
parent | b0d93c74d884b40bd94469a5ef75fdb2fef17680 (diff) |
Merge branch 'master' into modesetting-gem
Diffstat (limited to 'libdrm/intel')
-rw-r--r-- | libdrm/intel/intel_bufmgr.h | 1 | ||||
-rw-r--r-- | libdrm/intel/intel_bufmgr_gem.c | 16 |
2 files changed, 16 insertions, 1 deletions
diff --git a/libdrm/intel/intel_bufmgr.h b/libdrm/intel/intel_bufmgr.h index 1f7f73a4..e8c2e063 100644 --- a/libdrm/intel/intel_bufmgr.h +++ b/libdrm/intel/intel_bufmgr.h @@ -111,6 +111,7 @@ drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr, unsigned int handle); void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr); int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo); +void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable); /* drm_intel_bufmgr_fake.c */ drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd, diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c index 64d32d38..f7ad7571 100644 --- a/libdrm/intel/intel_bufmgr_gem.c +++ b/libdrm/intel/intel_bufmgr_gem.c @@ -738,9 +738,23 @@ drm_intel_gem_bo_get_subdata (drm_intel_bo *bo, unsigned long offset, return 0; } +/** Waits for all GPU rendering to the object to have completed. */ static void drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo) { + return drm_intel_gem_bo_start_gtt_access(bo, 0); +} + +/** + * Sets the object to the GTT read and possibly write domain, used by the X + * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt(). + * + * In combination with drm_intel_gem_bo_pin() and manual fence management, we + * can do tiled pixmaps this way. + */ +void +drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable) +{ drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr; drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; struct drm_i915_gem_set_domain set_domain; @@ -748,7 +762,7 @@ drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo) set_domain.handle = bo_gem->gem_handle; set_domain.read_domains = I915_GEM_DOMAIN_GTT; - set_domain.write_domain = 0; + set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0; do { ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain); } while (ret == -1 && errno == EINTR); |