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authorEric Anholt <eric@anholt.net>2010-03-17 10:05:55 -0700
committerEric Anholt <eric@anholt.net>2010-03-17 11:15:45 -0700
commit7c697b1670fe34b54a7b82d8ff0732845caa05a3 (patch)
treeda5b0ce87eedb2bb5bd2e006c45b15fb90aa17f4 /intel
parent30ce1fd1522ef266f172321438626813b78ed14c (diff)
intel: Align untiled buffer pitch to 64B.
This is the largest untiled pitch requirement from gen2 through gen4. It's only the case for gen3 rendering to color regions with depth, but it's rare for this to be a significant factor in memory usage -- for example, gen4 requires 1 or 2 times the element size, or up to 64 bytes depending on the size of the elements. This is easier than encoding all the various little quirks for untiled pitch alignment, since we rarely do untiled now.
Diffstat (limited to 'intel')
-rw-r--r--intel/intel_bufmgr_gem.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index c3b5d6ae..8e46e374 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -257,8 +257,11 @@ drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
unsigned long tile_width;
unsigned long i;
+ /* If untiled, then just align it so that we can do rendering
+ * to it with the 3D engine.
+ */
if (tiling_mode == I915_TILING_NONE)
- return pitch;
+ return ALIGN(pitch, 64);
if (tiling_mode == I915_TILING_X)
tile_width = 512;