intel: enable relaxed fence allocation for i915

The kernel has always allowed userspace to underallocate objects
supplied for fencing. However, the kernel only allocated the object size
for the fence in the GTT and so caused tiling corruption. More recently
the kernel does allocate the full fence region in the GTT for an
under-sized object and so advertises that clients may finally make use
of this feature. The biggest benefit is for texture-heavy GL games on
i945 such as World of Padman which go from needing over 1GiB of RAM to
play to fitting in the GTT!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

1 files changed, 12 insertions, 3 deletions

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index c5847a8a..37a3691c 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -99,9 +99,10 @@ typedef struct _drm_intel_bufmgr_gem {
 	int available_fences;
 	int pci_device;
 	int gen;
-	char has_bsd;
-	char has_blt;
-	char bo_reuse;
+	unsigned int has_bsd : 1;
+	unsigned int has_blt : 1;
+	unsigned int has_relaxed_fencing : 1;
+	unsigned int bo_reuse : 1;
 	char fenced_relocs;
 } drm_intel_bufmgr_gem;
 
@@ -243,6 +244,10 @@ drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
 		return size;
 	}
 
+	/* Do we need to allocate every page for the fence? */
+	if (bufmgr_gem->has_relaxed_fencing)
+		return ROUND_UP_TO(size, 4096);
+
 	for (i = min_size; i < size; i <<= 1)
 		;
 
@@ -2128,6 +2133,10 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
 	ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
 	bufmgr_gem->has_blt = ret == 0;
 
+	gp.param = I915_PARAM_HAS_RELAXED_FENCING;
+	ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
+	bufmgr_gem->has_relaxed_fencing = ret == 0;
+
 	if (bufmgr_gem->gen < 4) {
 		gp.param = I915_PARAM_NUM_FENCES_AVAIL;
 		gp.value = &bufmgr_gem->available_fences;