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authorEric Anholt <eric@anholt.net>2011-12-20 13:03:37 -0800
committerEric Anholt <eric@anholt.net>2011-12-29 16:43:29 -0800
commit1d318e2a79c3ae02fa886bcba79ac68b5222e1a3 (patch)
tree8d70ee343c8c7532f68d0dd513a2b164b2b5696b /intel
parent078bc5b6ee24ea786c465f5e29dcb8b0d2f81b2e (diff)
intel: intel: Add IS_GEN[567] macros.
These will be used by intel_decode.c, and were taken from intel-gpu-tools. Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Eugeni Dodonov <eugeni@dodonov.net>
Diffstat (limited to 'intel')
-rw-r--r--intel/intel_chipset.h38
1 files changed, 37 insertions, 1 deletions
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 5d417dab..e3a30fc7 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -28,6 +28,23 @@
#ifndef _INTEL_CHIPSET_H
#define _INTEL_CHIPSET_H
+#define PCI_CHIP_ILD_G 0x0042
+#define PCI_CHIP_ILM_G 0x0046
+
+#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */
+#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
+#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
+#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */
+#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
+#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
+#define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */
+
+#define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */
+#define PCI_CHIP_IVYBRIDGE_GT2 0x0162
+#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */
+#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
+#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
+
#define IS_830(dev) (dev == 0x3577)
#define IS_845(dev) (dev == 0x2562)
#define IS_85X(dev) (dev == 0x3582)
@@ -86,6 +103,24 @@
#define IS_GM45(dev) (dev == 0x2A42)
+
+#define IS_GEN5(dev) (dev == PCI_CHIP_ILD_G || \
+ dev == PCI_CHIP_ILM_G)
+
+#define IS_GEN6(dev) (dev == PCI_CHIP_SANDYBRIDGE_GT1 || \
+ dev == PCI_CHIP_SANDYBRIDGE_GT2 || \
+ dev == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
+ dev == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
+ dev == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
+ dev == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
+ dev == PCI_CHIP_SANDYBRIDGE_S)
+
+#define IS_GEN7(dev) (dev == PCI_CHIP_IVYBRIDGE_GT1 || \
+ dev == PCI_CHIP_IVYBRIDGE_GT2 || \
+ dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \
+ dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \
+ dev == PCI_CHIP_IVYBRIDGE_S)
+
#define IS_G4X(dev) (dev == 0x2E02 || \
dev == 0x2E12 || \
dev == 0x2E22 || \
@@ -96,6 +131,7 @@
#define IS_9XX(dev) (IS_GEN3(dev) || \
IS_GEN4(dev) || \
IS_GEN5(dev) || \
- IS_GEN6(dev))
+ IS_GEN6(dev) || \
+ IS_GEN7(dev))
#endif /* _INTEL_CHIPSET_H */