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authorEric Anholt <eric@anholt.net>2012-01-04 11:52:32 -0800
committerEric Anholt <eric@anholt.net>2012-01-27 13:21:19 -0800
commitb5cb7f88de249c6871b0e1d1e4005a7b1f54f088 (patch)
tree9b26fe1081fa9208bfd35389abdeeb5a15b13824 /intel/tests
parent66518ab5653cfdc840cd69e7b653ec05df060584 (diff)
intel: Add a regression test for 2D decode, which I'm about to refactor.
Diffstat (limited to 'intel/tests')
-rw-r--r--intel/tests/gen7-2d-copy.batchbin0 -> 56 bytes
-rw-r--r--intel/tests/gen7-2d-copy.batch-ref.txt14
l---------intel/tests/gen7-2d-copy.batch.sh1
3 files changed, 15 insertions, 0 deletions
diff --git a/intel/tests/gen7-2d-copy.batch b/intel/tests/gen7-2d-copy.batch
new file mode 100644
index 00000000..ce7fc292
--- /dev/null
+++ b/intel/tests/gen7-2d-copy.batch
Binary files differ
diff --git a/intel/tests/gen7-2d-copy.batch-ref.txt b/intel/tests/gen7-2d-copy.batch-ref.txt
new file mode 100644
index 00000000..0d621d37
--- /dev/null
+++ b/intel/tests/gen7-2d-copy.batch-ref.txt
@@ -0,0 +1,14 @@
+0x12300000: 0x54f08006: XY_SRC_COPY_BLT (rgb enabled, alpha enabled, src tile 1, dst tile 0)
+0x12300004: 0x03cc0190: format 8888, pitch 400, rop 0xcc, clipping disabled,
+0x12300008: 0x00000000: dst (0,0)
+0x1230000c: 0x00640064: dst (100,100)
+0x12300010: 0x122e9000: dst offset 0x122e9000
+0x12300014: 0x00000000: src (0,0)
+0x12300018: 0x00000080: src pitch 128
+0x1230001c: 0x02ff1000: src offset 0x02ff1000
+0x12300020: 0x13000002: MI_FLUSH_DW post_sync_op='no write'
+0x12300024: 0x00000000: address
+0x12300028: 0x00000000: dword
+0x1230002c: 0x00000000: upper dword
+0x12300030: 0x05000000: MI_BATCH_BUFFER_END
+0x12300034: 0x00000000:
diff --git a/intel/tests/gen7-2d-copy.batch.sh b/intel/tests/gen7-2d-copy.batch.sh
new file mode 120000
index 00000000..796ca5fe
--- /dev/null
+++ b/intel/tests/gen7-2d-copy.batch.sh
@@ -0,0 +1 @@
+test-batch.sh \ No newline at end of file